Hi Charles -
     
     One question: I would not expect a 13x4, 0.062, 8 layer assembly to be 
     overly "flexible" - are you experiencing the problem due to simple 
     handling or as part of a testing or stress screening operation?
     
     
     
     Dave Hillman
     Rockwell Collins
     [log in to unmask]
     


______________________________ Reply Separator _________________________________
Subject: Pins popping up
Author:  [log in to unmask] at ccmgw1
Date:    11/12/96 10:29 PM


Technet:
     
 I have a board about 13.5" x 4.5" (PC plug in card), .062" thick,
8 layer, FR4, 1 oz copper, 2 power planes, with 16  100 pin  TQFP 
packages (0.5mm lead pitch) spread across the board (2 rows of 8), as 
well as many other PLCC and SOIC devices.
     
 The problem we are having with these prototypes is that some pins
on the TQFP's pop up durring handling.  The boards seem to be too 
flexable, which probably causes the pins to break off the pads.  Is there 
a way to make the board more rigid besides using board stiffiners?  In 
other words can anything be done as far as changing the board stack up, 
or will using thicker copper help this situation?  Or are there different 
types of FR4 available?  Or is there something I am not looking at?
     
 Also, what would be a good pad size for the 100 pin TQFP chip? 
Currently I am using 1.2mm x .25mm, but I think the IPC recommends 1.6mm 
x .35mm, but it doesn't look like it would allow any soldermask between 
pads.  Or does anybody even bother with soldermask between pads at .5mm 
pitch?  What is the middle ground?
     
Thanks in advance!
     
Charles Wills
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