Concur with John.                           Bob Wilson CID+.
            Crane Aerospace

On Jan 20, 2017 5:40 PM, "John Parsons" <[log in to unmask]> wrote:

> Bill,
>
> From a fabrication perspective and assuming that you will want your V-I-P
> filled and capped (IPC-4761 Type VII) then cost should be a consideration.
> The additional processing required to produce a board that meets IPC wrap
> plating specifications (IPC-6012C, 3.6.2.11.1) can add considerably to the
> cost.
>
> Regards,
>
> John Parsons
>
> -----Original Message-----
> From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of
> Gebhardt, Bill
> Sent: January-20-17 7:17 AM
> To: [log in to unmask]
> Subject: [DC] Via In Pad technology
>
> I am trying to gain a better understanding of when to use (or not use)
> V-I-P technology.
>
> Can anyone tell me when it is NOT a good practice to use V-I-P
> technology?  What are the pros and cons to using them?  What about using a
> via for two components that are back-to-back (opposite sides of the board)
> which share the same net?
>
> A fellow designer, an EE (or two) and even a Director of Engineering at my
> place feels (strongly, I might add) that it is not good practice; that
> there are substantial risks with it that are not worth taking (based on
> info gleaned using Google).
>
> The layouts I do are primarily for airborne electronics.  The board in
> question is not too dense, so I am able to use standard technology in terms
> of via placement.  However, there are a few tight places where I readily
> used V-I-P, but...
>
> Any input/insights will be greatly appreciated!
>
> Bill Gebhardt, C.I.D. +
> PCB Designer
> Mission Systems
> General Atomics Aeronautical Systems, Inc.
> Bldg A03-1381D
> 16761 Via Del Campo Ct
> San Diego, CA  92127
>
> Office: (858) 762-5035
> Cell:  (909) 229-7824
> Fax:  (858) 762-5939
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