You are testing my memory.... but I think that the limitation has to do with the 'tooth' of the copper clad on either side of the core material and how deep it penetrates into the core... I'm sure someone will correct me if I'm wrong about that...
'Z-core' as I have heard it called, or Sanmina's ZBC material has a patent on making their 2 mil material... and I think the way they do it is by limiting the 'tooth' of the electroplated copper... so I think they sacrifice some of the copper adhesion for the thinner dielectric... and I would expect they might have more trouble with dendritic growth or what they call electro-migration thru imperfections in the material's dielectric.
They may have a 1.5 mil thick material as well, I have not looked at their materials in awhile...
Remember that IPC is a 'standard's ' organization... they build or collect consensus and then document and publish it... In no way does that limit what a designer can design... it just makes for good guidelines and common practice...
:)
William Brooks, CID+
Senior MTS (Contract)
2747 Loker Ave West
Carlsbad, CA 92010-6603
760-930-7212
Fax: 760.918.8332
Mobile: 760.216.0170
E-mail: [log in to unmask]
-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of Larry Brophy
Sent: Friday, February 07, 2014 11:12 AM
To: [log in to unmask]
Subject: [DC] Dielectric Thickness/Spacing IPC-2222A
In IPC-2222A 4.3.2 the minimum dielectric spacing defaults to 90 μm [0.00354 in]
Can the layer separation be reduced if we state that the biggest voltage difference between layers is a max of 24V (+12V and -12V being the largest positive and negative voltages on the board), can we get away with a smaller layer separation and still meet IPC Class 3? And if so what would be the minimum?
Many thanks for your help.
Larry Brophy
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