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February 2014

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Subject:	Re: Dielectric Thickness/Spacing IPC-2222A
From:	iTech iCollege iSrael מכללת טכנ <[log in to unmask]>
Reply To:	(Designers Council Forum) ולוגיות הייטק <[log in to unmask]>
Date:	Sun, 9 Feb 2014 13:28:57 +0200
Content-Type:	text/plain
Parts/Attachments:	text/plain (38 lines)

FR-4 has  a voltage withstand of  900 volts per mil (30,000 VOLTS per mm), see IPC2221 materials table. to be safe due to tolerance and aging effect I suggest to consider it as  300 volts per mil. or 1000 volts for 3.5 mil=90um. So you could reduce it to 3 um but the PCB manufacturer can't.  So ask your  PCB manufacturer for the most thinner core or prepreg he can use.
Shalom-Shlomi Zigdon  IPC2221 committee member, Lecturer for PCB Design for Signal Integrity & EMC Seminars
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-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of Larry Brophy
Sent: Friday, February 07, 2014 9:12 PM
To: [log in to unmask]
Subject: [DC] Dielectric Thickness/Spacing IPC-2222A

In IPC-2222A 4.3.2 the minimum dielectric spacing defaults to 90 μm [0.00354 in]

Can the layer separation be reduced if we state that the biggest voltage difference between layers is a max of 24V (+12V and -12V being the largest positive and negative voltages on the board), can we get away with a smaller layer separation and still meet IPC Class 3? And if so what would be the minimum?

Many thanks for your help.

Larry Brophy

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