In IPC-2222A 4.3.2 the minimum dielectric spacing defaults to 90 μm [0.00354 in]
Can the layer separation be reduced if we state that the biggest voltage difference between layers is a max of 24V (+12V and -12V being the largest positive and negative voltages on the board), can we get away with a smaller layer separation and still meet IPC Class 3? And if so what would be the minimum?
Many thanks for your help.
Larry Brophy
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