.int [log in to unmask]

 Are the  IPC standards for dimensions of etched feature to etched
 feature are too loose for todays fine pitch PWAs. Correct me if Im wrong, but
 I think the spec is +/- 5 mils for PWBs less than 12 inches and +/- 8 mils on
 larger PWBs. If we have a perfect stencil perfectly centered on a board that is
 8 mils too big, we have an error of 4 mils at each edge. If you have a 12 mil
 pad and stencil opening of 10 mils you will have a 5 mils of paste on the pad
 and 3 mils of the paste off the pad on devices near the edge of the board. We
 had one instance of this where our contract house couldn't produce the
 assembly. Now we also need to allow some tolerance for the stencil maker,
 something for the positioning of the stencil to the board and size changes from
 temperature differences from the FAB shop to the assembler. No wonder the
 defect rate for fine pitch is so much higher than 50 mil stuff.
  How accurate can the feature to feature be on a fab without a large cost
 penalty? Seems to me the spec should take into account the actual pad size. The
 larger the pad the more feature to feature error could be allowed. How does the
 rest of the would handle this to insure product can be built?

 Larry Sternig
 [log in to unmask]

 *** Original Author: ipc!ipc.org!TechNet-          10/19/95  101402

 Resent-Date: Wed, 18 Oct 1995 20:58:14 -0500
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 From: [log in to unmask] (Jerry Cupples)
 Subject: Re: PCB vs. Paste Stencil Comp

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 >From: Kelly Kovalovsky, PCB Quality Engineering
 >~     EMail:[log in to unmask]
 >Subject: PCB vs. Paste Stencil Comp
 >We have a fairly large circuit board that we are assembling. The card
 >has fine pitch SMT at extreme ends. We have noticed a mismatch between
 >the solder paste stencil and the printed circuit board. The circuit
 >board features are actually closer together than the stencil.
 >
 >My question to any card assembly site is whether it is common practice
 >to compensate a solder paste stencil for shrinkage of a PCB?

 Some may do so (never heard of it, myself), but we never do, and have some
 9U VMEbus boards as large as 16" x 16" (you metric folks, multiply by 2.54
 to get cm) with which we have not seen such problems.
 At the risk of demeaning someone from that tower of technology known as
 International Business Machines - no sarcasm in my voice, I assure you; we
 always (the last 2 yrs I've been here) send Gerber files directly to the
 stencil fab houses, and I think that the use of even 7 mil mylar stabilized
 film is inadvisable due to the possibility of image growth related to temp
 or humidty changes.

 We have had good success with laser cut stencils, and I think that one
 advantage they offer is that there is no film generation required to create
 diazos - they call them rubyliths, I think - as for chem etching. On larger
 panel sizes, it would seem film stability could be a concern. The laser
 burns metal according to the data provided, I have been told. They do seem
 to release paste noticeably better, as well. Ours come from Alpha Sigma in
 New Jersey so long as my budget permits. They run up to well over $500 for
 0.5 mm pitch (often called 20 mil by us Texans) cuts mounted in 18 x 18
 cast frames. If you contact your Alpha Metals rep, they might offer you a
 "free trial" to replace that questionable stencil.

 And then, there's the possiblity that board film had been
 "grown/shrunk"...You could try laying a mylar photoplot (we keep 'em for
 reference) of the layer 1 film on the stencil and checking it...

 Again, I would guess you knew this.

 cheers,

 Jerry Cupples
 Interphase Corporation
 Dallas, TX
 http://www.iphase.com