TECHNET Archives

1996

TechNet@IPC.ORG
Options: Use Monospaced Font
Show Text Part by Default
Show All Mail Headers

Message: [<< First] [< Prev] [Next >] [Last >>]
Topic: [<< First] [< Prev] [Next >] [Last >>]
Author: [<< First] [< Prev] [Next >] [Last >>]

Print Reply
Subject:
Assy: PCMCIA depaneling
From:
"Baldwin, Jeff A" <[log in to unmask]>
Date:
Wed, 16 Oct 96 13:03:00 DST
Content-Type:
text/plain
Parts/Attachments:
text/plain (20 lines) 

Hello.  We are looking at depaneling techniques for PC Cards.  We will 
probably be using a 3 board side-by-side design, and using pallets to help 
control warpage and handling issues.  Could anyone suggest an adequate score 
depth for an average 0.020" thick PCB?  If we were to use perforated tabs, 
could anyone suggest a hole size and spacing pattern?  Thank you for your 
help.

Jeff Baldwin
[log in to unmask]

***************************************************************************
* TechNet mail list is provided as a service by IPC using SmartList v3.05 *
***************************************************************************
* To unsubscribe from this list at any time, send a message to:           *
* [log in to unmask] with <subject: unsubscribe> and no text.        *
***************************************************************************

ATOM RSS1 RSS2