Bill thanks for the feedback. Actually the customer was not EAC but another
customer. The defects stated were found at in circuit or functional testing
and I believe that the component solder "open" counted only as one defect
even though both sides of the component leads (capacitor for example) may
have been unsoldered. The finish on these boards was HASL (or is that
HASSLE?) and the boards supplied are typically 20-25 mil pitch quad packs.

One of my concerns is that of reliability and reliable solder defect
repairs. Specifically, what the future bare board requirements may need to
evolve into to support my customers' needs. I estimate that the number of
SMD pads is approximately equal to the number of via holes, and at Circo we
drill half a billion holes per month, just in one division! Even at 10ppm
the number of potential repairs would be significant to say the least.

I am glad to see you pursuing OSP and/or alternative solderable finishes,
most of the pwb industry is striving to provide this, however, the flux and
soldering process seems to be the predominent constraint to short term
success. And flux/finish compatibility appears to determine OSP future
potential. 

I have received only a few responses, I'm not sure whether there are only a
limited number of assembly contacts on line (I am using both Technet and
Fabnet) or whether the data is perceived to be "taboo".

Dave


>In response to your posted questions concerning assembly yields, I would 
>like to offer several comments.
>
>The first issue pertains to the definition of "ppm".  I have encountered 
>several interpretations of this method of measuring yield.  If there is any 
>prevailing convention, it is to consider each component and each solder 
>joint as one opportunity for failure.  Hence, a more descriptive term is 
>dpmo, defects per million opportunities.  It should be noted that a number 
>of companies consider each component as two opportunities.  As you might 
>imagine, this can have quite a bearing on whether 25 is "above average" or 
>not.  What rules did your customer use?
>
>The complexity of the assembly also has a great deal to do with expected 
>yields.  Ultra fine pitch (<0.5mm), size of PCB, and board finish are just a 
>few factors.  In my experience, if the card has many fine and ultra fine 
>pitch components 25 dpmo could be an excellent yield.
>
>The effect of board finish is more significant with fine and ultra fine 
>pitch.  We have done enough work with ultra fine to not even bid on jobs 
>that require a HASL finish.  In addition, we prefer even our fine pitch to 
>use a flat finish (OSP or Au).
>
>The repair of a solder "open" is fairly simple but costs time and money.  I 
>would find it very difficult to believe they cannot repair opens; they just 
>may not want to ($).
>
>No-clean solders have a lower activity and hence will not overcome 
>variations in component solderability as easily as high activity pastes. 
> However, if their process is set up to run no-clean, you probably have 
>limited opportunity to change paste.
>
>The problem could actually be self-inflicted in another way: poor process 
>control of the solder paste application, placement, and reflow process.  I 
>assume they are probably a large OEM.  This does not necessarily mean they 
>have effective controls.
>
>If you really want to get into assembly yields issues, contact Charles-Henri 
>Mangin at CEERIS (806) 434-8740.  He does this type of work for a living and 
>is very knowlegable.  However, be prepared to pay for the info.
>
>I would be interested in sharing more information with you on this subject 
>if you wish.  It so happens we buy PCBs from your company (I hope we are not 
>the ones you are referring to!).  In addtion, I would be interested in 
>hearing about any other feed back you may have received.  Feel free to 
>contact me at your convenience.
>
>Bill Barthel
>Process Engineering Manager
>Electronic Assembly Corp (EAC)
>(414) 751-3651
>[log in to unmask]
>
>