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May 2006

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TechNet <[log in to unmask]>
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IPC TechNet <[log in to unmask]>
Date:
Fri, 12 May 2006 08:45:46 -0400
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TechNet E-Mail Forum <[log in to unmask]>, Phil Nutting <[log in to unmask]>
Subject:
Thermal stitching in SMT boards
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From:
Phil Nutting <[log in to unmask]>
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This was missed in my post yesterday.
 
Thermal Stitching;
We have an SMT power transistor that has about 16 thermal stitch holes
located directly under the device.  The adjacent pad area is taken up by
heat sink.  Is this "industry standard"?
 
Short of reading all the IPC standards... zzzzzzzz... oh sorry, I dozed
off there, is there a good source for coming up to speed on SMT and
board layout good standards?
 
Thanks in advance,
 
Phil Nutting

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