This was missed in my post yesterday. Thermal Stitching; We have an SMT power transistor that has about 16 thermal stitch holes located directly under the device. The adjacent pad area is taken up by heat sink. Is this "industry standard"? Short of reading all the IPC standards... zzzzzzzz... oh sorry, I dozed off there, is there a good source for coming up to speed on SMT and board layout good standards? Thanks in advance, Phil Nutting --------------------------------------------------- Technet Mail List provided as a service by IPC using LISTSERV 1.8e To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815 -----------------------------------------------------