Greetings Colleagues,

I have a question regarding Interfacial Connections, and an apparent
disparity between J-STD-001 and IPC-A-610.

Briefly, para. 9.2.5 of J-STD-001 states

"Plated through-holes without leads, including vias, after exposure to
reflow, wave, dip, or drag solder processing SHALL meet the
acceptability requirements ...."

However, IPC-A-610 states

".... after exposure to wave, dip, or drag soldering equipment shall
meet all ......"

Note, no reflow process mentioned in 610.

Vias will not have any solder applied with a reflow process unless the
stencil is manufactured that way.  None of our stencils has any
provision for applying solder to via holes.  Does this mean, in order to
comply, that we have to record every occurrence of this as a process
indicator?
  
Thanks in advance,

Ian J Graham,
Quality Manager.
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