Right. You need to have some pad left to solder the component to. Direct to
BGA is a pretty clear case where if you have via-in-pad, you have to cap.
On the other hand, for grounding vias beneath a QFN, the tiny bit of area
removed from the solder joint will have no effect on the performance for
nearly all applications.

The fill allows you to "cheat" by putting a via on the corner of an SMT
component pad without worrying about the open via thieving the solder, so
most often you don't need to even worry about the decrease in joint area.
Even on the BGA example, you can move from clear dogbones with a solder
mask between the via and BGA contact to the via hole edge being only 0.003"
from the pad edge with no worries.

It still gives the fabs a little more high skill work to do: While
aggressive sanding isn't necessary to reduce plating buildup due to the cap
plate, some kind of heavy duty cleaning/scrubbing is still needed to get
the fill residue off. They might try to economize on that by filling after
etching, but that can leave little over-fill nubs which interfere with the
planarity, messing up stencil printing of the solder.  So nothing's free,
but the process certainly contains a few less steps than the capped process.

Wayne Thayer

On Tue, Aug 27, 2019 at 4:34 PM Stephen Pierce <[log in to unmask]>
wrote:

> Area array pad over a plated via (blind or through) is the most common
> reason
>
> On Tue, Aug 27, 2019 at 3:49 PM Jack Olson <[log in to unmask]> wrote:
> >
> > When are caps on filled vias required by an application?
>