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Subject:
From:
Wayne Thayer <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Wayne Thayer <[log in to unmask]>
Date:
Sat, 24 Aug 2019 10:55:55 -0700
Content-Type:
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Dave-

I beg to differ....

Specifying caps when they aren't required by your application invites
unnecessary risk.

First, specifying anything which has no inherent benefit to the design is
poor "systems engineering" practice.

Second, plated caps aren't simply like asking for extra nuts on your ice
cream sundae: It specifies a completely different plating layup: If no
caps, the outer metal surface of all conductors and pads is plated at the
same time the via walls are plated. This is a very good thing since it is
easy to get plenty of "wrap" at the corner between the plated via and the
surface metal. If you demand plated caps, then two separate plating cycles
are needed. You may think that is no problem, but it creates a natural
place to crack the via rim. This is why IPC specifies a minimum "wrap
plate". This "wrap plate" is typically achieved by overplating a "doughnut"
around the via. That "doughnut" creates a bump on the top surface which
creates problems for photoresist, imaging, and etching. To reduce the bump,
fabricators use some kind of abrasive process to thin it down to close to
the IPC required minimum wrap plate. But that is a very difficult process
to control, and I have seen large variations in "wrap plate" across a panel.

Since most customers of fabricators don't seem to have the capacity to
understand the above, fabricators have responded by defaulting to plated
caps if you request complete fill.

Wayne Thayer

On Thu, Aug 22, 2019 at 10:39 AM Dave Schaefer <[log in to unmask]> wrote:

> Jack,
>
> Save yourself some trouble and spec VII filled and capped.
> Gives the added benefit of protecting from solder flow to opposite side
> during manufacture and the process requires all vias to be properly filled.
> My experience with other fill methods has never yielded acceptable
> results: either ended up with about 10% of vias not fully filled or with
> material seepage resulting in manufacturing issues due to the impact on the
> paste application process.
> Going from V to VII will cost slightly more (3-4% here) but that is
> insignificant in comparison to the costs of failures of assembled product.
>
> Hth,
> Dave
>

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