RE>Via-in-Pad for BGA                        12/8/95

Regarding Via-in-Pad for BGA:

I have some experience with this strategy, and I don't believe that it's all that necessary.  (At least, not for my company's applications.)

First of all, I think that you need to clarify which flavor of BGA you're using:  Ceramic, Tape, or Plastic.  With the first two, you'll generally find 90/10  Pb/Sn balls which have a stringent requirement for solderpaste volume on the pad.  VIPs can pull solder down into the barrel, which can weaken your joints.  I would not use this type of a via for these devices, unless you cap the top of the via (i.e., a blind via).

For the more common PBGA with eutectic balls, I believe that you have more freedom to do this, and I've actually seen successful use of VIP.  Granted, they had to be 8 mils finished diameter, so there's a significant PWB cost adder. 

We've been able to use a "dogbone" type of approach on both our CBGA (50 mil, orthogonal array) and PBGA (~71 mil pitch, interstitial array) devices, using 14 mil finished vias.  (We don't do ICT, so I can't comment on that point.)   As far as routing goes, we rotate the vias around the fixed BGA SMT pads to allow for centralized routing channels -- this helps to make routing to inner connections easier.  FYI, we've been using BGAs for over 2 years now.

I hope this helps!

Greg Bartlett
Mercury Computer Systems
Chelmsford, MA
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Via-in-Pad for BGA
Has anyone had experience with via-in-pad for BGA devices?  

As I see it, there are some advantages and disadvantages of the concept:

Advantages:
1)  Secondary-side test access for ALL nodes of the BGA, possibly eliminating
the need for an expensive clam-shell ICT test fixture.
2)  Less stressful BGA removal, since bottom-side heat will help liquify the
ball/solder interface EQUALLY over the entire IC without the need of extensive
component package heating.
3)  Trace routing for inside nodes can use any of several inner layers, thus
making line density (width and space) more manageable and NOT eat up top-side
PCB real estate.

Disadvantages:

1)  The via pattern does eat up inner layer and bottom-side PCB real estate.
2)  It does punch a lot of holes in the ground/power planes, making shielding
in the BGA area more difficult. 

Are there any other items to be considered before embarking on this bold
concept?  Does IPC cover this type of assembly with an industry "standard"? 

Bill Fabry
Truevision, Inc.
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