At 05:50 PM 10/22/99 -0700, Abd ul-Rahman Lomax wrote:
>At 03:25 PM 10/22/99 -0700, Douglas McKean wrote:
>>It's my opinion that the stackup S1/S2/G/P/S3/S4
>>is only an extension of a typical 4 layer stackup
>>S1/G/P/S2.  I don't think it would buy you anything.
>>If you're stuck with a S1/S2/G/P/S3/S4 stackup, then
>>you'd have to exercise great care with layout.
>
>Care with layout is advised in either case!

Understood.  My boss and I are trying to put together
a paper for an IEEE presentation where although one
achieves good SI, EMI can suffer by as much as 20dB.
A surprising result to say least and more investigation
has to be pursued.

In the case of a S1/S2/G/P/S3/S4 stackup, you might
have greater freedom moving a trace between S1 and
S2 without penalty EMIwise.  OTOH, while having to
move a trace between S1 and S2 on a S1/G/P/S2 stackup
might conform to good SI practices, but you might suffer
EMI-wise.  Far field prediction is one area where
simulators break down.  Far field prediction is
especially tricky.  And that's what I meant by exercising
great care in layout.  General rules of layout must not
be taken for granted for any stackup.

One question the original poster I believe alluded
to, maybe unintentionally, was the assignment of
what goes where for each layer.  What that question,
I'd assign from highest to lowest frequencies the
layers S1 to Sn respectively.  I have used this
practice with combined video and audio on the same
board with much success. And especially when confronted
with high speed digital circuitry.

One other general rule that may be applied is traces
can display as much as half the inductance by being
placed toward the center of the board as compared to
being placed toward the edge of the board. While
although this may make sense from a simple circuit
model analysis of said construction, this was finally
experimentally verified by Curtis & Straus within the
past year.

Comments greatly invited.

Regards,  Doug