At 11:46 AM 10/20/99 EDT, [log in to unmask] wrote:
>Hi,  I hope someone can help me out here.  I'm looking for suggestions on
>ways to quite down traces that we know are going to be noise generators.  If
>using a 6 layer board...what is the best stack up?  Should power and ground
>planes always be kept next to each other for optimum capacitive performance?
>Which layer should these noisy lines be kept on?  Any help?

Certainly the stackup  S1/G/S2/S3/P/S4 has been
used successfully.  I've seen successful stacking
with S1/G/S2/S3/<fill>/P/S4.  Lo freq stuff on S4
and hi freq stuff on S2.  Keep the P plane separated
from as many S planes as possible.  In this case, just
one signal plane is referenced to the power plane.
If you're talking just a small number of noisy traces,
then I'd personally prefer to bury them on S2.

It's my opinion that the stackup S1/S2/G/P/S3/S4
is only an extension of a typical 4 layer stackup
S1/G/P/S2.  I don't think it would buy you anything.
If you're stuck with a S1/S2/G/P/S3/S4 stackup, then
you'd have to exercise great care with layout.

But, strictly my opinion again.

I personally prefer stacking G and P planes right
together only when allowed with something like
8 layer stacks such as S1/G/S2/G/P/<fill>/S3/G/S4.
Or any extension of this.

I'm sure there's plenty of people on this forum
who could certainly talk more about this.

Something else you should consider is what's called
"partitioning".  Separate areas on the board for
specific functions - a digital area, an analog area,
off-board interface connection area, interface chip
area, etc ...

Just about any good book that delves into emc design
of the printed circuit board that's been mentioned
by previous posters should cover this topic.

Regards, Doug