Tim,

Do you have a problem with someone trying to get to the bottom of a
suspected discrepancy of such importance?  Maybe you just skip over issues
that you don't understand about your job, but I don't.  I like to know what
I am doing and why I am doing it.  If you have something constructive to add
to the discussion, I welcome it.  Otherwise, I'm sure Pegasus Mail has a
delete button somewhere.

Ray

----- Original Message -----
From: Tim D. Reid <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, September 21, 1999 2:20 PM
Subject: Re: [DC] IPC Specs - Errors?


> You can lead a horse to water, but you can also beat it to death.
>
> Date sent:              Tue, 21 Sep 1999 13:46:40 -0700
> Send reply to:          "DesignerCouncil E-Mail Forum."
<[log in to unmask]>,
>         Ray Humphrey <[log in to unmask]>
> From:                   Ray Humphrey <[log in to unmask]>
> Organization:           DynaCad Design Services
> Subject:                Re: [DC] IPC Specs - Errors?
> Originally to:          [log in to unmask]
> To:                     [log in to unmask]
>
> Gary,
>
> My comments to your latest follows....
>
> > This explanation will be a difficult one so here goes. The left hand
> > illustration in figure 5-18 indicates a minimum 0.010 inch clearance
> between
> > a land and its clearance in the plane. The purpose of this minimum has
to
> do
>
> This clearance is for a pad-to-plane, not an anti-pad.  I would presume
that
> it could be used for the OD of a thermal, too, since IPC-D-275 does not
> address this dimension.  (It does address the Web size, but not the
> clearance size between the inner pad and the surrounding plane.)  Consider
> this - If I design a Level A PCB with a maximum dimension of 12" inches,
> maximum voltage of 100V and use anti-pads (clearance pads) on the planes,
> they would need to be 90 to 92 mils in diameter.  However, if, rather than
> using anti-pads, I use a donut shape (pad with a clearance ring), it would
> have an ID of 60 mils and an OD of 80, still meeting all the requirements
> for clearance, including the electrical clearance.  If, according the the
> specs, they can keep the drill within a given tolerance for an internal
pad,
> then why would it need to be doubled for an anti-pad?  I ask that you set
> aside any pre-concieved ideas (as I did before I started this) and
consider
> the entire process of building a padstack, with all the tolerances given
in
> the specification.  It has been my experience that this is an area that
most
> designers do not fully understand.  Rather than spending the time
necessary
> (which most don't have) to ferret out the data, they just use what seems
to
> work, whether or not it is correct.  IPC could go a long ways in clearing
up
> this confusion and providing the data in a clear, easy-to-understand
format.
>
> > The input received by the committee is that the designer must design in
a
> > larger space, no less than 0.010 inch. this will enable the fabricator
to
> > obtain a more reliable inspection from his AOI equipment.
>
> This is true for, and applies to, PADS on the plane layer, not anti-pads.
> We have two seperate issues, here, which are getting confused.
>
> > Now let us relate it to the other examples in figure 5-18 which refer to
> > landless unsupported and supported holes. Obvious to us is that we
require
> a
>
> These are for the anti-pads (clearance pads) used for pins that are not to
> be connected to the plane.
>
> > minimum electrical space. We must also prevent the resulting space from
> > getting too small as to create a similar problem with the AOI systems.
We
> > attempt to accomplish this by requiring a reasonable fabrication
allowance
> on
> > each side of the hole. Granted, in fine line and space applications, the
> > spacing may become smaller than our 0.010 inch minimum. But in more case
> than
>
> The 0.010 inch minimum does not apply to anti-pads; only to PADS that are
on
> the planes.  In any case, if the drill is off by a majority or all of the
> fabrication allowance (whatever amount it is), the only clearance left
> around the hole is the electrical clearance, which is less than 0.010 inch
> for voltages up to 300V.  The data is wrong and needs a complete review.
>
> > Furthermore, I wish to draw your attention to paragraph 5.3.1.4 Edge
> Spacing.
> > This paragraph is concerned with copper spacing to a board edge. That
edge
> > can be an outside edge or the inside edge of a cutout in the board. An
> > unsupported hole may also be construed as a cutout. The paragraph
> indicates a
> > requirement of minimum electrical spacing plus 0.016 inch. The last
number
> > reflects a hard process allowance instead of the variable one used in
our
> > previous discussions. This is to ensure that from an electrical product
> > safety standpoint, that a conductor does not come too close to a board
> edge.
>
> This clearance has to do with the fact that board edges and cutouts are
> performed with routers and shears, extending several inches, in some
cases,
> which are not as accurate as a drill bit when drilling a hole.  Sometimes,
> the edges are V-scored or tab-routed and later broken apart by hand.  The
> additional clearance for board edges and cutouts, when the above is
consider
> ed, makes sense.
>
> > I would also like to point out that in IPC-2221 Generic Standard on
> Printed
> > Board Design, one of the replacements for IPC-D-275 that the Standard
> > Fabrication Allowance table has significantly changed.
>
> Has the amounts changed?
>
> > I hope that this helps clarify your concerns.
>
> Not yet.  I appreciate your continued attempt, but do believe the data to
be
> in error.  If you will take the time to run all the numbers and look at
all
> the data, I think you will agree.  I look forward to your findings.
>
> > Regards,
> >
> > Gary Ferrari
> > Executive Director
> > IPC Designers Council
> > 860-350-9300
>
> Ray Humphrey
> DynaCad Design Services
>