Tim,
Agreed, inner layers require additional clearance.  For pads on internal
layers, this allowance is covered with the reduced annular ring
specification in table 5-11 of IPC-D-275 and with the fact that you use the
maximum DRILLED hole size in the formula, rather than the FINISHED hole
size.  Notice that there is no additional fabrication allowance for internal
pads in table 5-10 or in the formula used to calculate the minimum pad size,
with the exception of which size to use for the hole.

If the formula is correct, as you say, then it is saying that the
fabrication allowance on inner plane layers needs to be TWICE that of
external or internal signal layers.  I don't believe this to be true.  Also,
don't forget that the inner plane layers also have the electrical clearance
to be added in for each side of the hole and they are using the maximum
drilled hole size, which adds another 2 to 4 mils.

Breakout, unless specified, is not acceptable.  Provided the PCB vendor
stays within the fabrication allowance specified (Producibility Level A, B
or C), there will be no breakout.  Even if there was, then how much?  The
purpose for adding the minimum annular ring to the fabrication allowance is
to insure that there IS a minimum annular ring, with no breakout.

Notice that for the minimum pad size example given (60-mil pad with a 40-mil
(finished) hole, up to 12" Level C PCB), the anti-pad on the plane layers
would be 70 to 72 mils for a PCB with a maximum voltage differential of
0-100V.  This provides 4 mils per side (+/- .004) for electrical clearance,
10 mils per side (+/- .010) for fabrication allowance, and 1 to 2 mils per
side for dilled (not finished) hole size.  This says that even if the drill
is off by 10 mils, the electrical clearance would be maintained  For a Level
A PCB, the fabrication allowance increases to 20 mils per side (+/- .020)!!!
(A 90 to 92-mil anti-pad!)   I could do that with a hand drill.

Ray Humphrey
DynaCad Design Services


----- Original Message -----
From: <Tim Easterling> <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, September 21, 1999 6:05 AM
Subject: Re: [DC] IPC Specs - Errors?


> Ray, I believe the formula is correct.
> If you  poll some of your pwb vendors I think you will
> find that they will request , if not require, additional clearance
> on the inner plane layers. If , due to a miss drilling you have
> tangency or breakout on an outer layer pad if may not render
> your boards to scrap.
> But if your plane clearance ( anti pad )is the same as your outer pad
> and you have break out, you will have shorts to the inner plane layer.
> The additional clearance of the anti pad will provide a better yield for
> your pwb vendor.
>
>
>
> Tim Easterling
> Cadd Manager Commercial Engineering
> SCI Systems Inc.
> 8600 S. Memorial Parkway MS 200
> Huntsville, Al. 35802
> (256)882-4426 (ph)
> (256)882-4700 x4426 (voicemail)
> (256)882-4304 (fx)
>