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December 1998

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Subject:
From:
Bill Davis <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Tue, 15 Dec 1998 09:24:08 -0800
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Todd:
I've read the emails surrounding your problem and have a couple of
comments based on soldering a 15 mil 256 pin TQFP down.
We found a couple of things along the way: First, in a prior life, I had
TI perform soldering tests on their palldium process. The packages came
from their Malaysia facility. The soldering results showed that they did
not exhibit solderability problems until they were below 200C.

Next: Our packages that we had trouble with came from ASE in Taiwan. One
of the short comings in the JEDEC MS-029 spec is that coplanarity is
subjective- we found that toe angle and toe length were two contributing
factors. The toe angle should be held <6 degrees. The JEDEC toe lengths
are not spec'd, but genereally come in a long and short length- you may
want to look at this aspect. The long toe length (can't remember the
precise measurement) did not work, because it accentuated any
non-planarity issues in the IC package.

We came across 3 other attributes: the first is moisture absorption of
the IC. Typically, this manifests itself with the device failing due to
the "popcorn" effect- water turning to steam during reflow and the
adherent steam causing pressures that rupture the package or disrupt the
bond wire continuity. There is a subtler side effect that occurs on fine
pitch packages however at lower absorption levels. The pressure escaping
tends to cause the corners to undergo a 'potato chip' effect and
actually will cause lifting of several mils.

The next was the stencil itself- we found that a 4 mil stencil thickness
was optimum- I would think a 5 mil would be appropriate for the 20 mil
packages you're using.

Last was the package attributes themselves. We found that our packages
had not been sufficently cured during their manufacture. In order to
ascertain this you would need a TMA or DTMA. The easiest way is to
program the equipment for two consecutive thermal runs and look at the
shift in Tg. This percentage of shift is a good approximation of cure.
Most IC packages that have been properly processed should evidence
something less than 2% shift.

Hope this helps...

> Bill Davis, Ph.D.
> Diamond Multimedia Systems
> Senior Scientist
> Tel. 408.325.7868
> Cell. 408.888.5650
> e-mail: [log in to unmask]
>
>


-----Original Message-----
From: Todd Ness [mailto:[log in to unmask]]
Sent: Monday, December 14, 1998 8:42 AM
To: [log in to unmask]
Subject: [TN] Fine-Pitch Soldering Problem


Technetters,

We are currently having soldering problems with a QFP 100 package
part. The part is a TI microprocessor component with a 0.0196" pitch.
The problem we are having with this part is we are getting
intermittent opens with corner leads. Other fine-pitch components on
this board solder fine. We have been building these boards for about 1
1/2  years in production with no problems until the last three months.
I found out that TI recently switched the lead plating for this part
from Tin/Lead to Nickel/Palladium. The solder paste we were using was
Kester OA 596. However, due to the inability of this paste to solder
to palladium parts, we switched to Kester OA 598. The profile was also
tweeked per Kester's recommendations for soldering to palladium leads.
All leads for this component and all other components on the board are
soldering fine with the new paste and new profile, except for some
intermittent opens on corner leads of the TI part with
Nickel/Palladium leads. Component leads for this part were inspected
prior to pick and place for coplanarity. Does anyone have any ideas of
what may be happening and any recommendations for eliminating this
problem.

Happy Holidays

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