AQS,Inc. is a CM located in N. California.

I have a customer that design their fab with a via hole in the center of
the surface mount land pattern for all of their capacitors. This condition
is creating a high rate of insufficient solder and/or no solder condition
for those locations.

I believe this is a design violation however, I do not know what criteria
to reference and what violation this condition would be.

I would like to respond back to my customer with some design for
manufacturing feedback. Can someone familiar with this issue please direct
me to the correct IPC reference specification.

Thank you,
Michael D. Meanor
Process Engineer

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