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October 1998

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Subject:
From:
"Reed, Randy" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Thu, 15 Oct 1998 16:16:45 -0700
Content-Type:
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text/plain (103 lines)
I thought a few words from an IST user may be appropriate.  Susan is
correct that the IST testing is a destructive test on a coupon pattern.
This is not to say the coupon could not be designed into an image, but
none of the board designers have not exercised this opportunity.  Board
fabricators know of a few customers that have designed impedance coupons
and/or registration coupons into their images.

Susan is not correct that a lengthy design cycle is required to
incorporate the IST coupon.  PWB Interconnect Solutions can supply a
coupon to meet your needs in 2 days for FREE.  I would say it is pretty
tough to beat this deal.  PWB Interconnects provides the electronic
files and a drawing.  I have had coupons designed in 24 hours on an
emergency basis.

True the IPC is having trouble completing the committee activity to
correlate the IST to thermal stress.  Sadly to say this shortcoming is
due to the committee and not the IST technology.  The problem is finding
test vehicles and aggressive leadership to drive the project to
completion.  Not much has happened in the committee the last 6 months
and the IPC-TM-650 test method is stalled in the committee.  Enough
said.

Those who own IST testers and use the test service are actively
developing and reporting on their activities.  Some of these activities
are to develop correlations to thermal shock testing, studying board
performance before and after assembly, process control of processes,
board supplier screens, next generation assessments, and technology
qualifications (i.e. direct plate and microvias) by OEMs.  The
technology is providing valuable information and the number of owners
and users are gradually growing.

If you have questions about IST, feel free to give me a call.

Randy Reed
Merix Corporation
503.992.4421

> ----------
> Sent:         Thursday, October 15, 1998 2:38 PM
> To:   [log in to unmask]
> Subject:      Re: [TN] ICT for bare boards
>
>
> >Date: Wed, 14 Oct 1998 16:03:28 -0400 (EDT)
> >From: [log in to unmask]
> >Subject: Re: [TN] ICT for bare boards
> >Sender: TechNet <[log in to unmask]>
> >To: [log in to unmask]
> >X-To: [log in to unmask]
> >Reply-to: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
> >Approved-By: [log in to unmask]
> >
> >Keep in mind the IST is destructive and can only be
> >performed on test coupons - not actual boards.
> >
> >It is not like a bare board continuity check.
> >
> >You would have to do a lot of upfront design work to
> >make certain that your coupons could be used in the
> >tester.
> >
> >While there has been some correlation testing performed with
> >thermal cycling/thermal shock type tests, the IPC is trying
> >to do a round robin to correlate with thermal stress testing.
> >However it is not going too well.
> >
> >
> >Susan Mansilla
> >Technical Director
> >Robisan Lab
> >
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> >
> >
>

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