Doug,
I attached several TechNet posts from about a year ago on IST for your
information.
Eric Yakobson
Alpha PC Fab
Orna and Yehuda wrote:
>
> Hi everyone,
> I just managed to dig through all the stuff on my desk and find the April
issue of CircuiTree. Among the articles
there was one about IST (=Interconnect Stress
>
> My questions to you:
> - Does anybody have any experience with this test and is willing to share
the knowledge ?
> - I understand that this method is supposed to allow a good distinction
between PTH failures and interconnect
failures (post separations), is that really so?.
> - Where can I find guidelines for designing a test method for IST?
>
> Thanks,
> Yehuda
>
> *************************************
> * Yehuda E. Weisz
> * e-mail: [log in to unmask]
> * Tel: 972-3-5240362
> ************************************
Yehuda,
1. Besides Bill himself I know that both Randy Reed of Merix and Octavian
Iordache
of Circo Craft have experience with the test system. Contact me off the
Technet if
you need contact information.
2. Very preliminary information that we (IPC Post Separation TG and PTV
Reliability
TG) have indicates that it does. Contact Lisa Williams of the IPC staff to
obtain
the Post Separation TG minutes from Expo ?97. These Task Groups are in the
process
of preparing a test plan that intends to verify this as well as correlate
the results
to the existing thermal stress (solder float) test. This test plan will
likely be
the main topic of discussion at the upcoming IPCWorks meeting in
Washington.
3. I am personally working on a proposed IPC-TM-650 Test Method (2.6.26)
that I can
send to you if you wish.
Brian McCrory
Chairman, IPC Testing Committee
Delsen Testing Laboratories, Inc.
1024 Grand Central Ave.
Glendale, CA 91201
Phone: 818 247 4106
FAX 818 247 4537
email: [log in to unmask]
URL: http://www.primenet.com/~delsen/
rooke @ TOTAL.NET
08/07/97 04:30 PM
To: TechNet @ IPC.ORG
Subject: Re: [TECHNET] FAB: IST
We have been using IST technology for a number of years now and find it
extremely beneficial in assessing the intrinsic reliability of plated
through holes. It has a benefit of being both a relatively rapid assessment
tool while at the same time permiting an analytical approach to failure
analysis. We routinely use it as one of the techniques to validate process
changes PRIOR to implementation.
The IPC has recently included IST test methodology in the IPC-TM-650
manual.
Dave Rooke
Circo Craft - Pointe Claire
A division of Viasystems
rooke @ TOTAL.NET
08/09/97 12:29 PM
To: TechNet @ IPC.ORG
Subject: [TECHNET] [FAB] IST WWW link
For those who are interested in IST testing, there is an interesting
reference at:
http://www3.sympatico.ca/gerard.gavrel/ist.htm
Dave Rooke
Circo Craft - Pointe Claire
a division of Viasystems
randyre @ FGMAIL01.MERIX.COM
08/08/97 02:37 PM
To: TechNet @ IPC.ORG
Subject: [TECHNET] Fab/Assy: IST Test Method
Merix Corporation has used the IST technology the past 8 months. We use
the technology to optimize the reliability of the products we offer.
The IST results are used in process baselining, process introduction,
and material introduction. Similar to Circo-Craft's comment, we
certify process and materials PRIOR to introduction into the
manufacturing process.
The IST journey for Merix began with a comprehensive acceptance test
plan. We verified the machine heated the coupons evenly and to the
required temperature. We also produced 3 lots of material with varying
level of separations (on purpose, not a random event). We gave 1/3 of
the coupons to PWB Interconnect Solutions and tested the remainder at
Merix. The equipment was repeatable from site to site and correctly
screened the levels of quality. The IST identified failures were
confirmed by thermograph imaging and microsection evaluation.
Merix has completed 10 reliability studies with varying material
combinations (FR4, Getek, teflon, composite lay-ups) and technologies
(PTH, blind vias, and microvias). The machine results have identified
problems that correlate to microsection results. A key component to
finding the defects by microsection is using thermograph imaging to ID
the defect location.
The current status of the technology is a few companies own the
equipment and some companies use the test service provided by PWB
Interconnects Solutions. IPC is slowly moving to evaluate the
repeatability of the technology and provide a standard test procedure
for the industry.
If you want discuss the technology in more detail, feel free to give me
a call.
Regards,
Randy Reed
Analytical Lab
Merix Corporation
503.359.9300 x5-4421
randy.reed @merix.com
> Approved-By: [log in to unmask]
> MIME-Version: 1.0
> Date: Wed, 14 Oct 1998 08:01:37 -0500
> From: Doug Jeffery <[log in to unmask]>
> Subject: [TN] ICT for bare boards
> To: [log in to unmask]
>
> Technet,
>
> Has anyone heard of "ICT for bareboards and what does it stand for?
>
> Recently this testing techneque was laid on one of my sales reps. I
> thought they were referring to ICT or in circuit testing done at the
> assembly level. He insists that they were referring to bare board
> testing beyond opens and shorts.
>
> Does anyone know of this testing and where I can find information about
> it?
>
> .
>
> Douglas C. Jeffery
> Pre-Production Engineering Manager
> Electrotek, Inc.
> PH: 414-762-1390
> Fax: 414-762-1510
> Email:
[log in to unmask]
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