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October 1998

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Subject:
From:
Douglas McKean <[log in to unmask]>
Reply To:
DesignerCouncil E-Mail Forum.
Date:
Tue, 27 Oct 1998 09:23:23 -0800
Content-Type:
text/plain
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text/plain (69 lines)
At 10:23 AM 10/27/98 -0500, Charles J Wills wrote:
>Why should 4 layer boards be avoided?
>
>Charles
>[log in to unmask]

Hi Charles,

The list of course was in terms of my personal
preference. I'm going to try to do this with
ASCII but it may not come out right.

Common question.  Hope I can do it some justice.

Assume a 4-layer board with two ICs and
one trace between them that is passed from
one side to the other side.

          Component Side

             trace
S1    IC#1 --->---+    +-->-IC#2
Gnd  ---------<---|----|--<-----
Pwr  ??? ---------|--<-|---- ???
S2   -------------+-->-+--------

          Solder Side

The signal comes out of IC#1 travel along layer S1.
Kirchoffs Laws dictate that for every current going
out, there has to be a current coming back. Notice
the "return current" arrow in the Gnd Plane just
below the current coming out of IC#1.  The current
has to seek a complete circuit.  Energy doesn't
come out of nowhere.  Notice also, that the current
going into IC#2 has also a return current in the
Gnd Plane.  All's well and good since the return
current is indeed in the ground plane where it
should be.

But wait.  Where is the return current for the
signal in S2???   It's in the Pwr Plane!

Bad.  Very bad.  How does that return current
get back to the source of the signal in IC#1?
Through the power plane.  Since the return
current is now in the power plane, it can affect
anything else in the power plane.

As this is done with more traces and more
complicated geometries, the problem just
gets worse.

Hope this helps.

Doug

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