Why should 4 layer boards be avoided?

Charles
[log in to unmask]



On Mon, 26 Oct 1998 11:08:39 -0800 Douglas McKean
<[log in to unmask]> writes:
>At 10:28 AM 10/26/98 +0800, you wrote:
>>Hi everybody,
>>1) Would like to gather more information for board layout for EMC
>especially for
>>high speed and mixed signals. Can any body submit your list or
>provide me
>with
>>place that i can get this information ?
>
>That's kinda tough.  Basic plan is
>
>1)  What is the stackup?
>2)  Stack higher to lower freq signal planes starting
>    from component side on down to solder side.
>3)  Avoid 4 layer boards (S1, GND, PWR, S2) unless you really
>    know what you're doing.
>4)  As few plane changes on a signal trace as possible.
>5)  Solid ground planes is the rule,
>    slicing up a ground plane is to be avoided.
>6)  Never cross a slit in the ground plane with a signal trace.
>7)  If you have a choice, partition your circuits into their
>    own areas on the board. Favor on-board high freq circuitry
>    toward the center of a board.  Favor off-board high freq
>    circuitry near it's connector.
>8)  Keep traces as short as possible.
>9)  Keep traces as straight as possible.
>10)  There can be a whole dissertation one way or the other
>    as to what kind of angles to use in traces.  I tend to
>    prefer angles no more than 45 degrees as the rule.
>11) NEVER reference controlled impedance traces to a power plane.
>...
>
>The list could go on and on.

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