What are the failure mechanisms for stacked chip components. If heat
dissipation is accounted for with stacking, then is it strictly stress
relief at the solder joints?
If it is stress relief at the solder joints, then why do IPC spec's
allow such bulbous joints for parts that aren't stacked?
Would the failure occur at the chip-to-board interface or at the
chip-to-chip interface? Has anyone actually found stacking to be a
problem or is it more of a theoretical argument?
We design RF systems and would like to stack chips (especially caps)
for tuning purposes.
Frank Hinojos
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