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Tue, 17 Mar 1998 18:24:17 -0600 |
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I have very little experience, but I have only seen Kirkendall voiding
mentioned with regard to the wire bonding process (typically the
gold-aluminum interfaces). From a wire bonding perspective, wouldn't
increasing the temperature or dwell time increase the possibility of
voiding since diffusion rates usually increase with increasing temperature?
George Harman has a few pages on Kirkendall Voiding in his "Wire Bonding in
Microelectronics..." book, but I don't know if you can apply the
information to soldering.
Hopefully someone else will have a better answer.
Dave Anderson
Medtronic, Inc.
Opinions are my own, and not necessarily those of my employer.
>>> "Yuen, Mike" <[log in to unmask]> 03/16/98 03:08pm >>>
As I know it, Kirkendall voiding is caused by rapid diffusion of gold
molecules. It was typically related to gold finishes. My question is:
What else can be done to reduce the formation of such void other than
reduce gold thickness?
How about increase dwell time at reflow soldering?
Regards
MIchael Yuen
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