I have very little experience, but I have only seen Kirkendall voiding mentioned with regard to the wire bonding process (typically the gold-aluminum interfaces). From a wire bonding perspective, wouldn't increasing the temperature or dwell time increase the possibility of voiding since diffusion rates usually increase with increasing temperature? George Harman has a few pages on Kirkendall Voiding in his "Wire Bonding in Microelectronics..." book, but I don't know if you can apply the information to soldering. Hopefully someone else will have a better answer. Dave Anderson Medtronic, Inc. Opinions are my own, and not necessarily those of my employer. >>> "Yuen, Mike" <[log in to unmask]> 03/16/98 03:08pm >>> As I know it, Kirkendall voiding is caused by rapid diffusion of gold molecules. It was typically related to gold finishes. My question is: What else can be done to reduce the formation of such void other than reduce gold thickness? How about increase dwell time at reflow soldering? Regards MIchael Yuen ################################################################ TechNet E-Mail Forum provided as a free service by IPC using LISTSERV 1.8c ################################################################ To subscribe/unsubscribe, send a message to [log in to unmask] with following text in the body: ################################################################ TechNet E-Mail Forum provided as a free service by IPC using LISTSERV 1.8c ################################################################ To subscribe/unsubscribe, send a message to [log in to unmask] with following text in the body: To subscribe: SUBSCRIBE TechNet <your full name> To unsubscribe: SIGNOFF TechNet ################################################################ Please visit IPC web site (http://jefry.ipc.org/forum.htm) for additional information. For the technical support contact Dmitriy Sklyar at [log in to unmask] or 847-509-9700 ext.311 ################################################################