...PCB fabrication will not be a problem ??
How does your PWB fab vendor propose to plate these holes [reliably]?
If there are "no external layer traces or connections...", isn't it a
blind via?
Anyway, this is very difficult to do, depending on the hole size...
FABRICATION:
In conventional outerlayer imaging, the circuitry and pads are
built concurrently with the PTH thickness. Consistent, voidless
plating demands (among other things) hydrodynamic chemistry
replenishment inside the holes, usually accomplished through
perpendicular agitation. Without agitation (or with a hole closed on
one side) the panel movement cannot easily 'flush' fresh solution
through the hole. To plate the PTV with only one pad requires
shrinking the imaged (photoresist) hole on the non-pad side to smaller
than the hole diameter (since artwork-to-drill pattern registration is
never perfect) thus partially tenting the hole and inviting solution
stagnation during Cu plating.
RELIABILITY:
The weak point will be introduced at the 'knee' where the
photoresist is draped over the hole wall and partially into the hole.
Fresh plating solution will have a tough time getting to this
interface with the outerlayer copper foil (is it half oz or 1 oz?).
If resist lam/expose/developing conditions were not ideal, the
potential for a rim void will exist at the top of the hole. Even if
there is no circuitry connected to the outerlayer pad, partially
choking off the hole may cause voids at innerlayer connections. With
pads on both sides of a PTV, you get a two-point connection to the O/L
copper foil, kind'a like a rivet. With one pad removed, you end up
with a circumferential connection limited to the thickness of the O/L
foil. On a .093" 14L, you undoubtedly have a high resin-to-glass
ratio, thus high thermal expansion at solder temperatures (and high
stress concentration on the barrel copper); this is what fractures
high-aspect ratio, weakly-plated vias.
SUGGESTION:
Drop the hole size (I'm assuming they're vias) down to a #77
(.018") or even #80 (.0135"), and the pads down to .025"-.030"
diameter, but for long-term reliability - keep the pads. [Please call
or e-mail if you're interested in further discussion].
ON THE OTHER HAND...
I invite further discussion from PWB fab shops on how padless vias
can be reliably made; it might be of some interest for producing
blind and buried, sequentially-laminated vias...
Joe Felts
PC World, Toronto
(416) 299-4000
[log in to unmask]
______________________________ Reply Separator _________________________________
Subject: ASSY - Padless Plated Thru Holes
Author: [log in to unmask] at INET
Date: 11/13/96 8:37 AM
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To extend clearance and eliminate potential shorts to the bottom
of a connector, the component side pad must be reduced to zero.
In other words,a top side padless PTH. The shorts are occuring during
wave solder.
What reliability down sides can we expect? Im advised that PCB
fabrication will not be a problem. Im mostly concerned with assembly
and repair operations.
Parameters: .093", 14 layer board
Finished hole .033" with solder side pad at .060"
No external layer traces or connections.
All connections are internal planes.
Thanks in advance: Ed Cassinelli =
Stratus Computer Inc
508-490-6821
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