just curious, did you send out for quote and have no takers?
On Sep 5, 2017, at 11:13 AM, Ricardo Moncaglieri wrote:

> Frank,
> Yours are unvaluable considerations for us.
> We are analyzing matter and will feed you back.....
> Thanks to all of you.
> brgds,Ricardo
>
>>>> Frank Kimmey <[log in to unmask]> 05/09/2017 11:50 >>>
> Ricardo,
> I see some concerns here definitely.
> Just a quick walk through of the processes looks like this design  
> would
> require a multiple lamination cycle and numerous plating cycles.
> I’ll try to explain:
> L3-L4 drill, plate and etch L3
> Laminate adding L2 then drill, plate and etch L2
> Laminate adding L1 then drill, plate and etch L1 and L4
> As you can see there would be 3 plate processes to put L4 through
> causing the need to planerize (remove copper) or etch to reduce  
> overall
> copper thickness. Also you will see considerable warpage due to almost
> all stress being added to the lower numbered layers as the stack up
> increases.
> I’m not sure you will have a lot of luck finding PCB Fabs willing to
> build this option.
> You might want to rethink the blind via options and maybe try buried
> for L2-L3 (you might be able to stagger a blind from L4 to L3 to make
> your L2-L4 connections), this would allow for 1 less lamination/plate
> process and may help with the stresses.
> Next thing to look at is the substrate, you want to mix a duroid
> material with a thermoset plastic material and bond them with adhesive
> film. This is doable but your final finish will play a role on how
> susceptible your finished PCB is to delam.
> Have you talked to you PCB Fab suppliers? They NEED to be involved  
> in a
> design such as yours if you want it successful.
> Let us know how it turns out or if we can help in any other way.
> Thanks and good luck,
> FNK
> Frank N Kimmey CID+
> Electrical Engineer / PCB Design
> VeriFone Inc
> 1400 W Stanford Ranch Road, Suite 200
> Rocklin, CA 95765 USA
> W: 1-916-625-1818
> M: 1-916-833-9877
> [log in to unmask]
> From: Ricardo Moncaglieri [mailto:[log in to unmask]]
> Sent: Tuesday, September 05, 2017 7:18 AM
> To: Richard D. Stadem <[log in to unmask]>; Frank Kimmey
> <[log in to unmask]>
> Subject: Re: FW: Multilayer PCB of Different Substrat Thickness RF
> Design
> Frank,
> Keep awaiting your feedback.
> Richard,
> Thank you for your assistance.
> brgds,Ricardo
>>>> "Stadem, Richard D." <[log in to unmask]> 05/09/2017 11:16
>>>>
> Frank, I can send the stackup directly to you, see it below.
> Richard
> From: Ricardo Moncaglieri [mailto:[log in to unmask]]
> Sent: Tuesday, September 05, 2017 8:34 AM
> To: Stadem, Richard D.; Steve Gregory
> Subject: Re: Multilayer PCB of Different Substrat Thickness RF Design
> Steve, Richard,
> Would you pls upload the herebelow quoted image inord to be more clear
> on my quetion to the forum?
> Indeed hope to receive your comments / advise.
> Keep awaiting.
> Thank you very much, brgds,Ricardo
> ---------------------------------------------------------------------- 
> ---------------------------------------------------------------------- 
> -------------------------------------------------
> Estimated colleagues,
> Nice to get in contact again with all of you after a bit long time.
> We are deploying a RF design and by first time we intend to use a
> multilayer pcb with different substrat thickness as shows the stack-up
> herebelow detailed.
> Questions here are:
> As per your experience, is it recomendable such a kind of substrat
> design?
> Some pcb provider reported it is very difficult to achieve. Can you
> recommend or share your background about pcb provider who can assure
> high reliability on this pcb provision?
> Keep awaiting for your unvaluable feedback.
> brgds, Ricardo
> Ricardo Moncaglieri
> QA Electronic Service Manager
> INVAP SE
> www.invap.com.ar
> *********************************************************
>