Please keep us posted on this.
We use the thermal vias in pad a lot. We do it in old fashion way - no fill or plug, reflow and manual fill of vias with a solder from the opposite side.
It is too much work. However, it is the cheapest and the most reliable solution. Everybody complaints, but do not want to try the newer methods that are available on the market due to the added cost to PWB:
1. Via filled, cap plated and planerized;
2. In via Solid Copper Plating (Via Systems and TTI do that).
Ones, we accidently received the board with the thermal vias filled with a soldermask. We ran one board through the reflow oven, than tried to build up the solder mound on the opposite side. The pad refused to take the solder evenly. Solder would not flow over the filled holes, but excess amount of solder was concentrating over the HASL covered areas. It took quite a bit of effort (and solder) to make the surface evenly coated.
It would be useful to do a microsection through the soldered component (we did not do it due to the added cost and therefor, a "global" luck of curiosity).
I suspect that there are many solder voids under the thermal pad of those power devices.
Regards,
Veronika Anderson C.I.D | Sr. Electrical/Mechanical Design Engineer | Excelitas Technologies
Office: +1 626-593-6025.
1330 East Cypress Street, Covina, CA 91724 USA
[log in to unmask]
www.excelitas.com
-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of Tom Brendlinger
Sent: Thursday, December 15, 2016 8:45 AM
To: [log in to unmask]
Subject: Re: [DC] Plugging Thermal Via Holes with Soldermask?
We recently used the following notes to attempt to do precisely what you're
describing:
12.2 All vias 0.020" in diameter or less shall be plugged from top side prior to primary soldermask application per IPC-4761 Type III. Plug material shall be approved by Levant engineering before production begins.
12.3 Plugs in vias shall not protude above top of hole.
12.4 All plugged vias shall be filled at least 80% with fill.
12.5 Via plug integrity, fill percentage and protrusion shall be confirmed with a microsection of a representative quality conformance coupon
However, after soldering about 30% of the at-risk holes had solder flow-through. We didn't see bumps, just a thin layer of wetting, but we only had 16 boards populated in this run so I don't think we have enough data to show that we never would have that issue.
I am currently working with our PCB manufacturer to identify what happened, but in my opinion this isn't a fully manufacturable solution. I'm attempting to solve the same problem that you are, so I'm absolutely interested in any other way to do this.
--
Tom Brendlinger, CID
Electrical Engineer
Levant Power / ClearMotion Inc
Woburn, MA 01801
On Thu, Dec 15, 2016 at 11:10 AM, Jack Olson <[log in to unmask]> wrote:
> I'm looking at the various options for tenting/plugging/capping vias
> in
> IPC-4761 (Via Protection Guidelines). None of the options seem to
> address the thermal vias in power pads.
> We are trying to:
> 1) have a solderable pad, apply paste on that side (of course)
> 2) prevent solder from creating bumps on the heatsink side (of course)
> 3) avoid the cost of plugging/capping
>
> IPC-4671 states that all forms of one-sided via protection are NOT
> RECOMMENDED.
>
> So here's the question - I know I have seen a picture of a thermal pad
> in an IPC document where I could see vias with green mask material in
> them on the paste side (the component side), but the green stuff was
> only in the holes, which left the thermal pad exposed for soldering.
> I don't think this would be called TENTING because there's no mask on
> the pad. but is this an acceptable practice? Can I instruct a bare
> board fabricator to put mask in holes from the top side, but keep the pad clear?
> (I can't remember where I saw the picture!)
>
> If that's NOT an accepted practice, is there a way to design the hole
> big enough to plate but small enough to prevent solder flowing through
> the other side of the board? I couldn't find a discussion of that in
> the TechNet Archives
>
> thanks,
> Jack
>
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