(1) those are part of AABUS I believe.
(2) did (long time ago and Before BlackBerry) have to specify supplier shall not use no-clean flux for balling and subsequently clean using solvents - reason is, no-clean surface oxidation are prevent proper clean, unless done aggressively - either by chemical or physical. You still risk to have trapped flux partially "cleaned".
(3) extraction may not be good enough. THB/pressure cooker bias for the package (daisy chained) style might be OK. Any change of sites of production, die shrink, etc. should be requal. Did have issues with change location and using lower grade of rinse DI water.
(4) when you deal with CSP, be careful about ionics if bottom cct is only protected by a thin layer of dielectrics (flip chip). If it is face up and with a silicon cap, not much of concern if item 2 is apply. - that also apply to PWB surface, the narrow spacing between the solder balls should be treated differently than the others.
(5) I can see two group divergent in the industry: class 3 stay with large format - no driving force to really go down to smaller form, fit, function. Only un-manned might have weight/format issue. But the risk factor (since it is un-manned= remove controlled)is not like aircraft before. The class 1 and 2 possibly using CSPs, due to handsets, but all depend upon the cost/supplier chain - usually not well controlled (some of them use 3rd party distribution house. You don't have any info about process details, what flux used for example. Not mention the locations, DI water purities, die size, etc.). It is very hard to draft a spec (so everybody can agree behind it... you wouldn't get enough vote for it). So AABUS might be the one if you have big stick to swing.
My 1.8 cents.
Joyce Koo
Researcher
Materials Interconnect Lab
Office: (519) 888-7465 79945
BlackBerry: (226) 220-4760
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of jrusseau.precisionanalysts.com
Sent: Tuesday, February 18, 2014 11:53 AM
To: [log in to unmask]
Subject: Re: [TN] Cleanliness testing at component level
Hello Phil,
I will chime in a little on this topic because I truly believe component cleanliness is an area that needs some exploration. I as the vice-chair of IPC's Ionic Conductivity task group have been pushing for a method specifically dealing with components. I will say that we are in the process of addressing this issue. What I can't say is what the acceptable limits for components might be. This is an area with little information available.
However, the only specification that I am aware of regarding component cleanliness testing tied to solder dipping of components leads is the GEIA-STD-006. The version I have has criteria defined based on the ROSE test methodology and virtually the same pass/fail criteria as defined in
J-STD-001 for assemblies. Now, I am not involved with the GEIA group effort and I don't know if a newer version exists with better criteria. However, IMHO the criteria that the GEIA document defines is meaningless, especially if you are using a "no clean" flux.
Best regards,
Joe Russeau
----- Original Message -----
From: "Phil Bavaro" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, February 18, 2014 11:30 AM
Subject: [TN] Cleanliness testing at component level
>I have reviewed the J-STD-001 several times but still have a question
>regarding a subcontractor who performs component level soldering operations
>for Class 3 hardware.
>
>
> If the subcontractor is performing a soldering operation, then cleaning is
> required to remove flux residues (this is not a no clean flux situation).
>
> If the subcontractor is cleaning, then cleanliness testing is required.
>
> The J-STD-001 does not really address the component level when it comes to
> the Post Soldering Cleanliness Designator (PSCD).
>
> If a component is having its leads pre-tinned or a BGA being re-balled,
> then is it defaulted to a C-22 PSCD?
>
> My position is yes but I can see where there might be arguments against
> this since the designator codes seem to speak to the assembly level and
> not the component level.
>
> My concern is that there is considerable time lag between when component
> soldering operations are performed relative to the actual PWA process
> which does get checked for cleanliness.
>
> Any input is appreciated.
> ________________________________
> This message and any attachments are solely for the use of the addressee
> and may contain L-3 proprietary information that may also be defined as
> USG export controlled technical data. If you are not the intended
> recipient, any disclosure, use or distribution of its content is
> prohibited. Please notify the sender by reply e-mail and immediately
> delete this message and any attachments.
>
> ______________________________________________________________________
> This email has been scanned by the Symantec Email Security.cloud service.
> For more information please contact helpdesk at x2960 or [log in to unmask]
> ______________________________________________________________________
>
______________________________________________________________________
This email has been scanned by the Symantec Email Security.cloud service.
For more information please contact helpdesk at x2960 or [log in to unmask]
______________________________________________________________________
______________________________________________________________________
This email has been scanned by the Symantec Email Security.cloud service.
For more information please contact helpdesk at x2960 or [log in to unmask]
______________________________________________________________________
|
