Dear All,

个人愚见将Reflow 翻译成回流焊，可以调查一下，虽然之前IPC标准已将它翻译为"再流
焊“，但业界到底有多少人在说“再流焊”呢？我觉得至少这一点
上，IPC 原先的翻译受到了挑战！ 似乎当时否定用“回流焊”的理由有点牵强。
我知道现在要改变，会牵涉到很多方面！

B／R
Charles.Lee




在 7/22/13 11:16 AM， "Porco Pan" <[log in to unmask]> 写入:

>Dear IPC會員大眾
>各位好,我是T-50中文翻譯技術組主席: 潘宏濤
>針對IPC-50H中文翻譯reflow為[再流焊]其實我個人是有不同意見,六年前當我還不是T-50主席時,其
實我也與IPC &業界眾多翻譯者,針對
>reflow做過激烈討論,不過當年志願者當中多數贊成翻譯為[再流焊]而且當時引述T-50的標準翻譯也是再
流焊,所以我當年也不便與大家爭論,畢竟我當時
>閱歷尚淺,人脈也不多,對業界狀況了解不夠自信
>去年底我正式接下T-50的技術文件翻譯主席工作,才發現這真是一件非常非常繁瑣,工作量超大和意義重大
的任務,因為T-50對眾多電子業內名詞翻譯有著高影
>響力
>回歸正題
>Reflow的英文原意(Webster's Online Dictionary)
>
>Reflow may refer to:
>
>1. Reflow soldering, the most common means to attach a surface mounted
>component to a circuit board.
>2. HTML Reflow, the process by which the geometry of the layout engine's
>formatting objects are computed.[1]
>"Notes on HTML Reflow", Mozilla, accessed 21 May 2007.
>
>我個人認為reflow指的是加熱方式,也就是熱風的流動(細節可以參考下列過去十年間reflow字的使
用方式)
>所以SMT設備名稱從最早的IR oven(紅外線烤箱) => IR reflow(紅外線熱風烤箱) => reflow (
熱風回流焊接爐)
>而flow指的就是風的流動, reflow指熱風在加熱爐中回流
>所以我個人決定將會在T-50J的例行翻譯周會中提出修正此翻譯方式(此例會中也包含多位不同IPC規範
的技術組主席),一旦通過reflow翻譯為回流焊
>,將全面改寫IPC所有技術文件的翻譯方式,屆時如有影響各位業界朋友慣用語時,請大家包涵並支持正確的
翻譯,謝謝
>
>Select Timeline: reflow
>Year Event  
>1991 Louisiana State Univ. Medical Center: Sponsored research
>"Experimental Brain Missile Wound: Ascertaining Pathophysiology and
>Evaluating Treatments to Lower Mortality and Morbidity. - Annual rept. 14
>Apr 90-13 Apr 91 (Final)." Sponsored by: Louisiana State Univ. Medical
>Center, New Orleans. Written by M. E. Carey. Abstract: Cerebral ischemia
>does not occur following a brain wounding provided that ICP is < 60 mmHg.
>Rather focal hyperperfusion occurs. Mechanical and chemical control of
>CBF are disturbed following brain wounding but these disturbances have
>wide regional variations. The missile-wounded brain may show severe CBF
>reductions with even a mild fall in MABP. No reflow follows cerebral
>ischemic occurring after brain wounding. Brain wounding is associated
>with decreased brain stem and hypothalamic biogenic amines especially
>epinephrine. This seems to be a part of a generalized stress response.
>Free radicals appear in the brain within minutes of brain injury.
>Additional references: Louisiana State Univ. Medical Center, Experimental
>Brain Missile Wound, Ascertaining Pathophysiology and Evaluating
>Treatments, Lower Mortality and Morbidity, Final. Sponsored, Louisiana
>State Univ, Medical Center.
> 
>1991 Furukawa Electric Co. Ltd.: Sponsored research "Furukawa Review No.
>9, August 1991." Sponsored by: Furukawa Electric Co. Ltd., Tokyo (Japan).
>Abstract: Partial Contents: InGaAs/GaAs Strained Layer Quantum Well
>Lasers; Nb3Sn Compound Superconductors for Use in High-Field Magnets;
>Thermal Cycling Behavior of Ni-Ti-Cu Shape Memory Alloy Coil Springs;
>Mechanical Properties of Al-Li Alloys; Recrystallization Behavior
>Following Hot Rolling of Al-Mn Alloys; A High-Performance Titanium
>Heat-Transfer Tube; Efcell Semiconductive Expanded Polypropylene Foam
>Sheet; Properties of Heat-Resistant Aluminum-Alloy Conductors for
>Overhead Power-Transmission Lines; A Fault-Location System for Overhead
>Power Transmission Lines; Transmission Cables for Local Area Networks;
>Cables For Audio Systems; Large-Current Composite Printed Circuit Boards
>for Large Power Applications; Development of a Bevel Roll Mill;
>Development of Reflow Furnace. Additional references: Partial Contents,
>GaAs Strained Layer Quantum Well Lasers, Nb3Sn Compound Superconductors,
>Field Magnets, Performance Titanium Heat, Transfer Tube, Efcell
>Semiconductive Expanded Polypropylene Foam Sheet, Properties of Heat,
>Resistant Aluminum, Alloy Conductors, Overhead Power, Location System,
>Overhead Power Transmission Lines, Transmission Cables, Local Area
>Networks, Current Composite Printed Circuit Boards, Large Power
>Applications, Bevel Roll Mill, Development of Reflow Furnace.
> 
>1992 Sandia National Labs.: Sponsored research "Evaluation of the blind
>lap joint for the surface mount attachment of chip components." Sponsored
>by: Sandia National Labs., Albuquerque, NM.; Department of Energy,
>Washington, DC. Written by P. T. Vianco and J. F. Dal Porto. Abstract:
>Blind lap solder joints were used to attach leadless ceramic chip
>resistors to polyimidequartz circuit boards. Hand soldering and vapor
>phase reflow techniques were evaluated. The solder was 62Sn-36Pb-2Ag
>(wt.%). The integrity of the solder joints was assessed by
>microstructural examination and room temperature shear tests. These
>analyses were performed on as-fabricated circuit boards as well as an
>those samples exposed to thermal cycling (308 cycles; (minus)55(degree)
>to 125(degree)C; 6(degree)C/min ramps; 120 min hold periods;) or thermal
>shock (100 cycles, (minus)55(degree)C to 125(degree)C; liquid-to-liquid
>transfer; 10 min hold periods). In all cases, microscopy revealed no
>cracks within the solder joints. The shear strengths of the joints were
>13.4 lb (59 N), as-fabricated; 10.5 lb (47 N), 308 thermal cycles; and
>14.0 lb (62 N), 100 thermal shock cycles. All values were well within
>acceptability limits for the particular application. Measurements of the
>intermetallic compound thicknesses at the copper land/solder interface
>indicated that the additional heating cycle of the hand soldering step
>decreased the layer thickness as compared to non-hand soldered joints.
>The successful implementation of the blind lap joint can provide
>increased device densities on circuit boards by reducing bonding pad
>extension beyond the ceramic chip foot print. Additional references:
>Department of Energy.
> 
>1993 Oesterreichisches Forschungszentrum Seibersdorf G.m.b.H.
>Hauptabteilung Angewandte Physik.: Sponsored research "Kontamination von
>Fluessigmetall-Indium Ionenemittern (Contamination of Liquid Metal Ludium
>Ion Emitters)." Sponsored by: Oesterreichisches Forschungszentrum
>Seibersdorf G.m.b.H. Hauptabteilung Angewandte Physik. Written by A.
>Sieber, M. Fehringer, F. G. Ruedenauer and W. Steiger. Abstract: Liquid
>metal indium ion emitters (LMIS), burning against a stainless steel
>collector exhibit gradual changes in operating parameters. For a voltage
>stabilized emitter, the current is slowly decreasing; for a current
>stabilized emitter, the operating voltage is increasing. These
>instabilities may cause problems during long-time operation of an LMIS,
>e.g., in space applications. Regeneration of such poisioned emitters
>(high operating voltage at given current) usually is possible by
>operating the LMIS at elevated current for a short time. Poisioning is
>attributed to contamination of the emitter needle by material
>backsputtered from collector and electrodes. Electron microprobe analysis
>of a needle clearly shows high concentrations of Fe and Cr with exception
>of the apex area, where the indium is clean. The contaminations freeze in
>plate-like structures under which indium is flowing towards the apex. Due
>to breakage of the plates and reflow of indium, the metal film on the
>needle is a multilayer film, indium-rich layers alternating with
>contamination-rich layers. Additional references: Indium Ionenemittern,
>Oesterreichisches Forschungszentrum Seibersdorf G.m.b, Hauptabteilung
>Angewandte Physik.
> 
>1993 Army Armament Research and Development Center: Sponsored research
>"Solderability of Surface Mount Devices." Sponsored by: Army Armament
>Research and Development Center, Dover, NJ. Fire Support Armament Center.
>Written by N. S. Holder. Abstract: As electronic products become much
>smaller, a limiting factor in the reduction of product size has been the
>size of electronic components which make up the product. The leads of the
>current electronic components are inserted onto a printed circuit board
>through holes. Due to the use of wire leads, it becomes more difficult to
>decrease the size of the components. A new method was created to mount
>components directly to the surface of the printed circuit board. This new
>technique is surface mount technology. A concern over the use of this is
>experienced by the military. Since the leads are not inserted through the
>board and crimped before soldering as conventional components are
>mounted, there is some regard as to whether the components can be mounted
>securely to the board. Due to the high forces that many munitions
>experience when dispensed, it is imperative that the electronic
>components be soldered to the circuits boards so they will not slip out
>of place or fall from the board. The military also requires many
>munitions to lie dormant in storage warehouses for up to 20 years. When
>the munition is needed, it must perform reliably. Little work has been
>done to study the effects of this long-term storage on these surface
>mount devices particularly the ability of different soldering techniques
>used to attach surface mount components to printed circuit boards to
>withstand damaging effects of long-term storage. Surface mount
>technology, Solderability, Wave soldering, Reflow soldering, Conductive
>adhesive curing, Long-term storage, Accelerated age testing. Additional
>references: Solderability of Surface Mount Devices. Sponsored, Army
>Armament Research and Development Center, Fire Support Armament Center.
> 
>1993 Sandia National Labs.: Sponsored research "Logistics for the
>implementation of lead-free solders on electronic assemblies." Sponsored
>by: Sandia National Labs., Albuquerque, NM.; Department of Energy,
>Washington, DC. Written by P. T. Vianco and I. Artaki. Abstract: The
>prospects of legislative and regulatory action aimed at taxing,
>restricting or banning lead-bearing materials from manufactured products
>has prompted the electronics community to examine the implementation of
>lead-free solders to replace currently used lead-containing alloys in the
>manufacture of electronic devices and assemblies. The logistics for
>changing the well established ''tin-lead solder technology'' require not
>only the selection of new compositions but also the qualification of
>different surface finishes and manufacturing processes. The
>meniscometer/wetting balance technique was used to evaluate the
>wettability of several candidate lead-free solders as well as to
>establish windows on processing parameters so as to facilitate prototype
>manufacturing. Electroplated and electroless 100Sn coatings, as well as
>organic preservatives, were also examined as potential alternative
>finishes for device leads and terminations as well as circuit board
>conductor surfaces to replace traditional tin-lead layers. Sandia
>National Laboratories and AT&T have implemented a program to qualify the
>manufacturing feasibility of surface mount prototype circuit boards using
>several commercial lead-free solders by infrared reflow technology.
>Additional references: Department of Energy.
> 
>1994 Allied-Signal Aerospace Co.: Sponsored research "Survivability of
>soldered leadless chip carriers after temperature cycling." Sponsored by:
>Allied-Signal Aerospace Co., Kansas City, MO. Kansas City Div.;
>Department of Energy, Washington, DC. Written by L. R. Zawicki, B. W.
>Lenhardt and F. R. Smith. Abstract: Temperature cycling evaluations were
>conducted on leadless chip carriers (LCCs) soldered to thick film
>networks (TKNs). Various temperature ranges, rates of change, cycle
>times, number of cycles, and sizes of LCCs were used. The TKNs were
>attached to metal backing plates with 63Sn/37Pb solder preforms using an
>infrared vacuum soldering process. The LCCs were attached to Pt/Au TKNs
>with 63Sn/37Pb solder paste using a belt reflow process. Visual
>examination and cross-sectional analysis were used to evaluate the
>survivability. Results were also correlated with finite elemental
>analysis. Considering the initial results, possible solutions included
>changing the solder from 63Sn/37Pb to 50Pb/50In, deleting the metal
>backplate, changing the rate of change in the temperature cycle, and/or
>adding leads to the large LCCs. Because of a system requirement, the rate
>of change in the temperature cycle could not be changed. Since there was
>no long term reliability information on the Pt/Au TKN with 50Pb/50In
>solder, this option was also dropped. Additional evaluations showed
>little difference in the survivability of large LCC solder joints with or
>without the metal backing plate. The final results indicated that LCCs
>beyond a certain physical size required compliant leads to survive the
>temperature cycle requirements. Additional references: Kansas City,
>Department of Energy.
> 
>1994 Sandia National Labs.: Sponsored research "Temperature-humidity-bias
>aging technique to identify defective surface mount capacitors."
>Sponsored by: Sandia National Labs., Albuquerque, NM.; Department of
>Energy, Washington, DC. Written by R. Chanchani. Abstract: Ceramic chip
>capacitors can potentially crack due to thermal stresses in a surface
>mount assembly process. The electrical performance of the cracked
>capacitors will degrade with time, and they will prematurely short. In
>high reliability applications, the cracked capacitors must be identified
>and eliminated. We have developed and demonstrated the
>temperature-humidity-bias (THB) aging technique to identify cracked
>capacitors. The initial phase of the study involved setting up automated
>test equipment to monitor 100 surface mounted capacitors at 85% relative
>humidity, 85(degree)C with 50 volts dc bias. The capacitors subjected to
>severe thermal shock were aged along with control samples. Failure mode
>analysis was done on the failed capacitors. The capacitors with surface
>cracks short-out within the first 8 hours of aging, whereas the
>capacitors that failed after a longer aging time (8 to 1000 hours) had a
>shorting path in an internal void. Internal voids are typical defects
>introduced during manufacturing of multilayer ceramic (MLC) capacitors.
>In the second phase of the study, we used the THB aging technique to
>study the effect of surface mount processes on capacitor cracking and,
>thus the reliability. The surface mount processes studied were vapor
>phase, infra-red (IR) and convection belt reflow soldering. The results
>shoed that 6.3% of vapor phase soldered capacitors, and 1.25% of the IR
>and convection belt soldered capacitors had cracks. In all capacitors,
>regardless of the solder process used, an additional 3 to 4% of the
>capacitors failed due to a shorting path in the internal void. The
>results of this study confirm that this technique can be used to screen
>cracked capacitors and compare different solder and manufacturing
>processes. Additional references: Department of Energy.
> 
>1994 Lawrence Livermore National Lab.: Sponsored research "Automated
>fiber pigtailing technology." Sponsored by: Lawrence Livermore National
>Lab., CA.; Department of Energy, Washington, DC. Written by O. T. Strand,
>M. E. Lowry, S. Y. Lu, D. C. Nelson and D. J. Nikkel. Abstract: The high
>cost of optoelectronic (OE) devices is due mainly to the labor-intensive
>packaging process. Manually pigtailing such devices as single-mode laser
>diodes and modulators is very time consuming with poor quality control.
>The Photonics Program and the Engineering Research Division at LLNL are
>addressing several issues associated with automatically packaging OE
>devices. A furry automated system must include high-precision fiber
>alignment, fiber attachment techniques, in-situ quality control, and
>parts handling and feeding. This paper will present on-going work at LLNL
>in the areas of automated fiber alignment and fiber attachment. For the
>fiber alignment, we are building an automated fiber pigtailing machine
>(AFPM) which combines computer vision and object recognition algorithms
>with active feedback to perform sub-micron alignments of single-mode
>fibers to modulators and laser diodes. We expect to perform sub-micron
>alignments in less than five minutes with this technology. For fiber
>attachment, we are building various geometries of silicon microbenches
>which include on-board heaters to solder metal-coated fibers and other
>components in place; these designs are completely compatible with an
>automated process of OE packaging. We have manually attached a laser
>diode, a thermistor, and a thermo-electric heater to one of our
>microbenches in less than 15 minutes using the on-board heaters for
>solder reflow; an automated process could perform this same exercise in
>only a few minutes. Automated packaging techniques such as these will
>help lower the costs of OE devices. Additional references: Department of
>Energy, Engineering Research Division.
> 
>1995 Allied-Signal Aerospace Co.: Sponsored research "Telemetry
>engineering and fabrication alternative soldering techniques for CFC
>elimination." Sponsored by: Allied-Signal Aerospace Co., Kansas City, MO.
>Kansas City Div.; Department of Energy, Washington, DC. Written by R. V.
>Howard. Abstract: In an effort to eliminate the need for chlorinated
>fluorocarbons (CFCs) for several production assemblies in Telemetry
>Engineering and Fabrication, an alternate soldering reflow process to
>replace the current vapor phase system was needed. After analyzing IR,
>convection, and recovery vapor phase soldering reflow methods, it was
>discovered that an improved process would result from the implementation
>of a new convection reflow system. The convection oven reflow method was
>evaluated by collecting data from visual inspections, shear, push, and
>cross-section tests on several surface mount devices. Additional
>references: Kansas City, Department of Energy, Telemetry Engineering and
>Fabrication.
> 
>1996 Sandia National Labs.: Sponsored research "Cost comparison modeling
>between current solder sphere attachment technology and solder jetting
>technology." Sponsored by: Sandia National Labs., Albuquerque, NM.;
>Department of Energy, Washington, DC. Written by R. N. Davidson.
>Abstract: By predicting the total life-cycle cost of owning and operating
>production equipment, it becomes possible for processors to make accurate
>and intelligent decisions regarding major capitol equipment investments
>as well as determining the most cost effective manufacturing processes
>and environments. Cost of Ownership (COO) is a decision making technique
>based on inputting the total costs of acquiring, operating and
>maintaining production equipment. All quantitative economic and
>production data can be modeled and processed using COO software programs
>such as the Cost of Ownership Luminator program TWO COOL(trademark). This
>report investigated the Cost of Ownership differences between the current
>state-of-the-art solder ball attachment process and a prototype solder
>jetting process developed by Sandia National Laboratories. The prototype
>jetting process is a novel and unique approach to address the anticipated
>high rate ball grid array (BGA) production requirements currently
>forecasted for the next decade. The jetting process, which is both
>economically and environmentally attractive eliminates the solder sphere
>fabrication step, the solder flux application step as well as the furnace
>reflow and post cleaning operations. Additional references: Department of
>Energy, Cost of Ownership Luminator, Cost of Ownership, Sandia National
>Laboratories.
> 
>1996 Allied-Signal Aerospace Co.: Sponsored research "Characterization of
>printing and laser trimming of DuPont 2000 series resistors on DuPont 951
>(open quotes)Green Tape(trademark)(close quotes)." Sponsored by:
>Allied-Signal Aerospace Co., Kansas City, MO. Kansas City Div.;
>Department of Energy, Washington, DC. Written by H. Morgenstern, S.
>Bandler and G. Barner. Abstract: DuPont 2000 series resistors were
>reviewed and found to come closest to our requirement of 1% resistor
>tolerance over the expected 30-year life of our products. The evaluation
>performed involved the characterization of both the printing and trimming
>processes. The printing process was characterized for firing temperature
>print thickness, print direction, resistor geometry and encapsulant
>effect. Laser trimming was characterized by first finding an operating
>envelope and then selecting an operating point. The envelope was located
>by varying the trimming parameters and determining their acceptability to
>electrical and visual criteria. Samples from both the envelope and
>operating point were environmentally conditioned The conditioning
>included thermal shock temperature cycle, 1000-hour temperature aging,
>1000-hour humidity aging, and a simulated gold/tin solder reflow.
>Additional references: Green Tapetrademarkclose, Kansas City, Department
>of Energy.
> 
>1996 National Physical Lab.: Sponsored research "Influence of
>Solderability on Reliability in Electronic Assemblies." Sponsored by:
>National Physical Lab., Teddington (England).; Department of Trade and
>Industry, London (England). Written by C. Hunt. Abstract: The impact of
>solderability degradation on solder joint fatigue is discussed and
>exemplary data on ceramic chip resistors are given. Components were
>exposed, prior to assembly, to six ageing regimes to modify the
>solderability of the surface finish. Following the accelerated ageing for
>various times at 155 degrees C, components were assembled using no-clean
>reflow soldering. The solder fillets on these components ranged from
>unacceptable non-wetting to excellent wetting. The process yield was
>correlated with the solderability. Assemblies were then thermally cycled
>between -20 and 100 deg C. The results revealed that the thermal fatigue
>failure rate, as measured by electrical continuity of the resistors, is
>correlated with solderability. The relationship between solderability and
>solder fillet shape, and hence process yield, has been demonstrated, and
>in turn solderability and yield has been correlated with thermal fatigue
>properties. (Copyright (c) 1996 Crown.). Additional references: Influence
>of Solderability, Electronic Assemblies. Sponsored, Department of Trade
>and Industry.
> 
>1997 Sandia National Labs.: Sponsored research "Development of a hybrid
>microcircuit test vehicle for surface mount applications." Sponsored by:
>Sandia National Labs., Albuquerque, NM.; Department of Energy,
>Washington, DC. Written by C. L. Hernandez, F. M. Hosking and P. T.
>Vianco. Abstract: The technology drivers of the electronics industry
>continue to be systems miniaturization and reliability, in addition to
>addressing a variety of important environmental concerns. Surface mount
>technology (SMT) has evolved in response to these issues. Prototype
>hybrid test vehicles have been developed at Sandia National Laboratories
>to evaluate three lead-free solders for Au-Pt-Pd thick film soldering.
>The alloys are based on the Sn-Ag, Sn-Ag-Bi, and Sn-Ag-Bi-Au systems.
>Populated test vehicles with surface mount devices were designed and
>fabricated to evaluate actual solder joints. Pastes were screen printed
>on the test substrates and reflowed with the components in place. The
>test components consist of a variety of dummy chip capacitors and
>leadless ceramic chip carriers (LCC's). The development of the reflow
>profiles is discussed. Comprehensive defect analysis is also presented.
>Additional references: Department of Energy, Sandia National Laboratories.
> 
>1997 Allied-Signal Aerospace Co.: Sponsored research "Investigation into
>environmentally friendly alternative cleaning processes for hybrid
>microcircuits to replace vapor degreasing with 1,1,1-trichloroethane.
>Final report. - PROGRESS REPT." Sponsored by: Allied-Signal Aerospace
>Co., Kansas City, MO. Kansas City Div.; Department of Energy, Washington,
>DC. Written by B. E. Adams. Abstract: Two cleaning processes, one aqueous
>and one nonaqueous, were investigated as potential replacements for the
>vapor degreasing process using 1,1,1 trichloroethane (TCA) for hybrid
>microcircuit assemblies. The aqueous process was based upon
>saponification chemistry. A 10% solution of either Kester 5768 or
>Armakleen 2001, heated to 140 F, was sprayed on the hybrid at 450 psig
>and a flow rate of 5 gpm through a specially designed nozzle which
>created microdroplets. The nonaqueous process was based upon dissolution
>chemistry and used d-limonene as the solvent in an immersion and spray
>process. The d-limonene solvent was followed by an isopropyl alcohol
>spray rinse to remove the excess d-limonene. The aqueous microdroplet
>process was found to be successful only for solder reflow profiles that
>did not exceed 210 C. Furthermore, removal of component marking was a
>problem and the spray pressure had to be reduced to 130 psig to eliminate
>damage to capacitor end caps. The d-limonene cleaning was found to be
>successful for solder reflow temperature up to 250 C when using a
>four-step cleaning process. The four steps included refluxing the hybrid
>at 80 C, followed by soaking the hybrid in d-limonene which is heated to
>80 C, followed by spray cleaning at 80 psig with room temperature
>d-limonene, followed by spray cleaning at 80 psig with room temperature
>IPA was developed to remove residual flux from the hybrid microcircuits.
>This process was the most robust and most closely matched the cleaning
>ability of TCA. Additional references: PROGRESS REPT. Sponsored, Kansas
>City, Department of Energy.
> 
>1998 USDOE: Sponsored research "Solder flow over fine line PWB surface
>finishes." Sponsored by: USDOE, Washington, DC. Written by F. M. Hosking
>and C. L. Hernandez. Abstract: The rapid advancement of interconnect
>technology has stimulated the development of alternative printed wiring
>board (PWB) surface finishes to enhance the solderability of standard
>copper and solder-coated surfaces. These new finishes are based on either
>metallic or organic chemistries. As part of an ongoing solderability
>study, Sandia National Laboratories has investigated the solder flow
>behavior of two azole-based organic solderability preservations,
>immersion Au, immersion Ag, electroless Pd, and electroless Pd/Ni on fine
>line copper features. The coated substrates were solder tested in the
>as-fabricated and environmentally-stressed conditions. Samples were
>processed through an inerted reflow machine. The azole-based coatings
>generally provided the most effective protection after aging. Thin Pd
>over Cu yielded the best wetting results of the metallic coatings, with
>complete dissolution of the Pd overcoat and wetting of the underlying Cu
>by the flowing solder. Limited wetting was measured on the thicker Pd and
>Pd over Ni finishes, which were not completely dissolved by the molten
>solder. The immersion Au and Ag finishes yielded the lowest wetted
>lengths, respectively. These general differences in solderability were
>directly attributed to the type of surface finish which the solder came
>in contact with. The effects of circuit geometry, surface finish,
>stressing, and solder processing conditions are discussed. Additional
>references: USDOE, Sandia National Laboratories.
> 
>1999 Sandia National Labs.: Sponsored research "Soldering of Thin
>Film-Metallized Glass Substrates." Sponsored by: Sandia National Labs.,
>Albuquerque, NM.; Department of Energy, Washington, DC. Written by F. M.
>Hosking, C. L. Hernandez and S. J. Glass. Abstract: The ability to
>produce reliable electrical and structural interconnections between glass
>and metals by soldering was investigated. Soldering generally requires
>premetallization of the glass. As a solderable surface finish over
>soda-lime-silicate glass, two thin films coatings, Cr-Pd-Au and NiCr-Sn,
>were evaluated. Solder nettability and joint strengths were determined.
>Test samples were processed with Sn60-Pb40 solder alloy at a reflow
>temperature of 210 C. Glass-to-cold rolled steel single lap samples
>yielded an average shear strength of 12 MPa. Solder fill was good.
>Control of the Au thickness was critical in minimizing the formation of
>AuSn(sub 4) intermetallic in the joint, with a resulting joint shear
>strength of 15 MPa. Similar glass-to-glass specimens with the Cr-Pd-Au
>finish failed at 16.5 MPa. The NiCr-Sn thin film gave even higher shear
>strengths of 20-22.5 MPa, with failures primarily in the glass.
>Additional references: Soldering of Thin Film, Metallized Glass
>Substrates. Sponsored, Department of Energy.
> 
>2001 Helsinki Univ. of Technology: Sponsored research "Formation of the
>Intermetallic Compounds Between Liquid Sn Different Cu-Ni Metalization."
>Sponsored by: Helsinki Univ. of Technology, Espoo (Finland). Dept. of
>Electrical and Communications Engineering. Written by V. Vuorinen, T. M.
>Kohonen and J. K. Kivilahti. Abstract: Interfacial reactions between
>liquid tin and different Cu-Ni alloy metallizations as well as the
>subsequent phase transformations during the cooling were investigated
>with the emphasis on microstructures of the reaction zones. It was found
>out that the extent of microstructurally complex reaction layer during
>the reflow at 240 degrees C does not depend linearly on the Ni content of
>the alloy metallization. On the contrary, when nickel is alloyed with
>copper, the rate of the thickness change of the total reaction layer
>first increases and reaches the maximum at the composition of about 10
>at-% Ni. The reaction layer is composed of continuous and relatively
>uniform (Cu,Ni)6Sn5 reaction layer, a uniphase layer, next to the NiCu
>metallizations and followed by the two-phase solidification structures
>between the uniphase layer and tin matrix. The thickness of the two-phase
>layer, where the intermetallic tubes or fibers have grown from the
>continuous interfacial (Cu,Ni)6Sn5 layer varies with the Ni-to-Cu ratio
>of the alloy metallization. In order to explain the formation mechanism
>of the reaction layers and their observed kinetics the phase equilibria
>in the tin-rich side of the SnCuNi system at 240 degrees C was evaluated
>thermodynamically by utilizing the available data and the results of the
>Sn/CuxNi. Additional references: Helsinki Univ. of Technology, Dept. of
>Electrical and Communications Engineering.
> 
>2002 California State Univ.: Sponsored research "Structure and Kinetics
>of Sn Whisker Growth on Pb-free Solder Finish." Sponsored by: California
>State Univ., Los Angeles.; Lawrence Livermore National Lab., CA.;
>Department of Energy, Washington, DC. Written by W. J. Choi, T. Y. Lee
>and K. N. Tu. Abstract: Standard leadframes used in surface mount
>technology are finished with a layer of eutectic SnPb for passivation and
>for enhancing solder wetting during reflow. When eutectic SnPb is
>replaced by Pb-free solder, especially the eutectic SnCu, a large number
>of Sn whiskers are found on the Pb-free finish. Some of the whiskers are
>long enough to become shorts between the neighboring legs of the
>leadframe. How to suppress their growth and how to perform accelerated
>test of Sn whisker growth are crucial reliability issues in the
>electronic packaging industry. In this paper, we report the study of
>spontaneous Sn whisker growth at room temperature on eutectic SnCu and
>pure Sn finishes. Both compressive stress and surface oxide on Sn are
>necessary conditions for whisker growth. Structure and stress analyses by
>using the micro-diffraction in synchrotron radiation are reported.
>Cross-sectional electron microscopy, with samples prepared by focused ion
>beam, are included. Additional references: Pbfree Solder Finish.
>Sponsored, Department of Energy.
> 
>2003 Texas Univ. at Austin. Dept. of Mechanical Engineering.: Sponsored
>research "Surface Over-Melt during Laser Polishing of Indirect-SLS Metal
>Parts. - Conference proceedings." Sponsored by: Texas Univ. at Austin.
>Dept. of Mechanical Engineering. Written by J. A. Ramos, D. L. Bourell
>and J. J. Beaman. Abstract: Laser polishing of indirect-SLS parts made
>from 420 stainless powder infiltrated with bronze has been achieved using
>CO2 and Nd:YAG lasers. Two mechanisms have been previously proposed for
>the reduction in surface roughness, namely: shallow surface melting (SMM)
>and surface over-melt (SOM). In SMM reflow of the molten surface
>minimizes the peak-valley height driven by capillary pressure and liquid
>curvature. On the other hand, during SOM the melting depth is such that
>the entire surface becomes liquid and formation of surface periodical
>structures dominates driven by a surface tension gradient. This surface
>morphology was identified by means of optical and scanning electron
>microscopy (SEM). The onset of this regime is dictated by the energy
>density (i. e., ratio of laser power to scan speed and beam diameter) as 
>well as the initial roughness R(a) value prior to laser surface 
>polishing. In contrast with SMM, onset of the latter mechanism increases 
>the roughness R(a) with speed reduction. A thermo-physical model is 
>presented, signaling good agreement with roughness R(sub a) and 
>characteristic surface wavelength results obtained for varying laser beam 
>scan speeds. Understanding the surface over-melt mechanism is critical 
>for determining the optimum polishing conditions that minimize roughness. 
>Additional references: Surface Over, Laser Polishing of Indirect, Texas 
>Univ, Dept. of Mechanical Engineering.
> 
>2003 Systran Federal Corp.: Sponsored research "Aerospace Sensor 
>Component and Subsystem Investigation and Innovation-2 Component 
>Exploration and Development (ASCSII-2 CED) Delivery Order 0003: 
>Hermetically Sealed Cavities in 3-D GaAs-Silicon and Silicon-Silicon 
>Packages for Microelectromechanical System (MEMS) Devices Using Selective 
>and Large-Scale Bonding. - Final rept. 7 Sep 2001-6 Sep 2002." Sponsored 
>by: Systran Federal Corp., Dayton, OH. Written by A. P. Malshe. Abstract: 
>Chip-scale bonding of GaAs-to-silicon and silicon-to-silicon to produce 
>cavities for 3-D assembly of MEMS devices has been demonstrated using 
>SnAgCu and eutectic SnPb solders. Laser and furnace reflow were used for 
>region- selective and fast bonding of the chips, respectively, for 3-D 
>assembly. For example, for GaAs-to-silicon bonding, lines of solder 
>paste, 150 mm in width, were screen-printed onto silicon wafers to form 
>square-shaped sealing rings as small as 2 by 2 mm. The solder line width 
>was optimized to provide the smallest width, yet sufficient to ensure a 
>hermetic seal. The solder was reflowed, and the wafer was diced into 
>individual chips of various die sizes. The chips were then flipped onto 
>gold-coated GaAs chips and again placed in the reflow oven at a 
>temperature of up to 250 deg C for a total reflow time of 7 minutes. The 
>bonded chips were then tested for hermeticity using MIL-STD-883E and by 
>examining the sealed area after the separation of the chips using a pull 
>test. For the case of selectively laser-bonded silicon-to-silicon chips, 
>the structures exhibited excellent hermetic it and adhesion stren th with 
>a uniform microcavity and uniform reflow of the solder. Additional 
>references: Hermetically Sealed Cavities, Silicon and Silicon, Silicon 
>Packages, Microelectromechanical System, MEMS Devices Using Selective and 
>Large, Scale Bonding.
>
>
>Best Regards
>Porco Pan 
>Director
>EBG CIPO Continue Improve Program Office
>Plant 1 Process Mechanical Engineering / Quality Assurance Department
> Wistron InfoComm (Zhongshan) Corporation
>Cell phone: +86 15016168852
>Extension: +86 760 23382382 #2858
>Enterprise internal mobile number: 63888
>
>-----Original Message-----
>From: TGAsia [mailto:[log in to unmask]] On Behalf Of Leesha PENG Lixia
>Sent: Saturday, July 20, 2013 9:56 AM
>To: [log in to unmask]
>Subject: [TGAsia] 回复: [TGAsia] 答复: 为什么取名为回流焊-Reflow
>
>英文中表示资金、人口回流意思的是哪个单词？似乎不是reflow吧。
>
>
>Peng Lixia
>GM, show&conference
>IPC Greater China
>
>
>Wellington Li <[log in to unmask]> 写道：
>虽然怎么翻译都能理解。但是用社会学、经济学领域的含义来解释科技词汇，是否很有说服力？
>
>窃以为不能因为“reflow”是个通用词汇就刻意回避和挑选汉字。这一点，IT行业就做的比我们好，Bug
和Bus的翻译都很经典！
>
>Reflow在日本业界也有这两种翻译方法，但“回流焊”被更广泛使用。
>
>Best regards
>
>Wellington Li 李永江
>Assessor  审核员
>British Standards Institution 英国标准协会
>
>发件人: TGAsia [mailto:[log in to unmask]] 代表 Liang, Abao
>发送时间: 2013年7月19日 13:47
>收件人: [log in to unmask]
>主题: Re: [TGAsia] 为什么取名为回流焊-Reflow
>
>有前辈纠正，以下的解释我觉得才是正确的：
>
>＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝
>回流焊/再流焊都是从英文reflow, 翻译而来。SMT工艺通过锡膏的reflow完成焊接这个过程。英
文Reflow 是相对于波峰焊，也称之为 
>flow soldering而来的。手工焊接第一次叫flow solder，而补焊动作(touch up)让原处的焊料发
生reflow.
>中文翻译也有用重熔焊的。业界使用更为普遍的似乎是回流焊，但是回流这个词是一个通用词汇，一种流
动趋势朝着与原来相反的方向流动，如人口，资金等等。术语标
>准组经过讨论，reflow 是再次的意思，而没有回头的意思。所以在IPC T50术语中使用了再流。
>＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝
>
>Abao.Liang
>
>________________________________
>From: [log in to unmask] [mailto:[log in to unmask]]
>Sent: 2013年7月19日 13:33
>To: Liang, Abao; [log in to unmask]
>Subject: RE: 为什么取名为回流焊-Reflow
>我觉得这个解释比较合理，热风回流，传导热量而起到焊接效果…..再流焊的叫法无法理解.前天在讨论标
准J-STD-033时，我就提起要改再流焊为回流
>焊，因T50的定义是再流焊，而没有被采纳。
>
>
>
>Best Regards
>Steven Hao | SMT Engineer Leader  | T +86 760 88923578-5583 | M +86 
>13531856616
>
>From: TGAsia [mailto:[log in to unmask]] On Behalf Of Liang, Abao
>Sent: Thursday, July 18, 2013 1:03 PM
>To: [log in to unmask]
>Subject: Re: [TGAsia] 为什么取名为回流焊-Reflow
>
>名称一般是取对象的特点来命名
>
>回流焊的特点是，发热器加热空气，空气流动并传导热量使得焊料融化而焊接起来，就叫做回流焊。
>
>那么为什么不叫做空流焊，热流焊，那个前辈解释一下？
>
>顺便问一下回字有四种写法...是怎么写的？
>
>
>Abao.Liang
>
>________________________________
>From: TGAsia [mailto:[log in to unmask]] On Behalf Of Zhong Mary
>Sent: 2013年7月18日 12:30
>To: [log in to unmask]<mailto:[log in to unmask]>
>Subject: Re: [TGAsia] 为什么取名为回流焊-Reflow
>可参阅IPC-T50
>
>意思就是：先将焊料加热至焊料流动，再使其冷却，所以叫回流焊
>
>Best regards!
>
>Mary Zhong
>IPC training specialist
>[Enics]<http://www.enics.com/>
>Phone: +86 512 590 0668-8055
>Mobile: +86 134 0142 0110
>
>
>
>[http://remote.neway.ee/download/Enics/icon_green.gif] Please consider 
>the environment before printing this email
>
>
>
>
>
>From: TGAsia [mailto:[log in to unmask]] On Behalf Of Fenglei Mao
>Sent: Thursday, July 18, 2013 12:12 PM
>To: [log in to unmask]<mailto:[log in to unmask]>
>Subject: Re: [TGAsia] 为什么取名为回流焊-Reflow
>
>百度啊
>
>Thanks,
>Fenglei
>
>From: TGAsia [mailto:[log in to unmask]] On Behalf Of Tao Qinfang 
>(AE/PJ-MFG-CN)
>Sent: Thursday, July 18, 2013 12:04 PM
>To: [log in to unmask]<mailto:[log in to unmask]>
>Subject: [TGAsia] 为什么取名为回流焊-Reflow
>
>Dear All,
>
>各位高手,能不能请教一下为什么取名为回流焊-Reflow,谢谢!
>
>Best regards | Mit freundlichen Grüßen | BeQIK Tao Qinfang AE-CN Academy
>Phone: +86 512 6767 7999
>
>
>
>
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