Hi William,
Indeed we don't want to fill thermal vias with solder but we had wicking issues as solder overflowed out of the plane of the other board side, creating uneven
surface (due to bulge formation) and inducing bad surface contact with printing stencil or heatsink.
Studying the thermal via diameter impact have shown us better results with 0.5mm rather than 0.4mm. Let me precise we are using lead-free solder.
It is just our experience.
But perhaps someone (or you) has different experience ?
Rgds
Grandrien
========================================
Message du 18/09/12 17:23
De : "Brooks, William"
A : [log in to unmask]
Copie à :
Objet : Re: [DC] Vias under a QFN package (Thermal Refief)
Hi Grandrien,
There's a 'sweet spot' for wicking... if that's what you are trying to accomplish. There are papers written about solder wicking for thru hole devices. But this
discussion is about vias for thermal transfer. We don't really want them to wick much.... otherwise if they do wick a lot you will 'solder starve' the device you are
trying to solder to the board. You really want them to not wick and leave the solder on the 'belly' pad where it is most useful.
Actually a gentleman I worked with, Patrick Weber, Sr. Mechanical Engineer at Datron World Communications ran thermal simulations on printed circuit vias and
found that the presence of solder in the holes was negligible as a contributor to the thermal transfer characteristics of the thermal vias... it's the amount of
copper that makes the biggest difference. Thicker copper in the barrel has a huge influence over the thermal transfer characteristics. If you check you will find
that solder isn't really a very good thermal transfer medium. He published a paper on the subject I think back a number of years ago...
At any rate, that's why you want the small vias with thick copper in the holes... more than an ounce of copper is much, much better. Try for 1.5 ounces or 2
ounces of copper in the holes...
You will see a vast improvement in the thermal transfer keeping the part cooler. The solder in the holes doesn't really help much at all...
And don't make the mistake I see so many inexperience folks make of assuming that they can heat sink the vias to the internal planes of the board with no other
provisions... pumping heat into the planes of a board only changes the thermal 'rise time' of the temperature of the part... it does not magically cool the part if there
is no path to the ambient air...The hot par will eventually reach thermal equilibrium or even thermal runaway and the part will overheat and fail. Internal planes in a
board are like a big bucket... if you keep pouring water (heat) into it, eventually it fills up and overflows... you need a path for the heat to get out of the box to the
air like putting a hose in the bottom of the bucket to let the water pass thru and out to the stream in order to not overflow the bucket... and fail...
William Brooks, CID+
Senior MTS (Temp)
2747 Loker Ave West
Carlsbad, CA 92010-6603
760-930-7212
Fax: 760.918.8332
Mobile: 760.216.0170
E-mail: [log in to unmask]
-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of grandrien
Sent: Tuesday, September 18, 2012 6:13 AM
To: [log in to unmask]
Subject: Re: [DC] Vias under a QFN package (Thermal Refief)
Sorry not to be totally convinced. We had exactly opposite results. Actually with 0.5mm plated via diameter we had less wicking than with 0.4mm diameter vias
under DPAK, QFN...
The root cause according to us must be capillary actions.
No results with 0.3mm.
Nobody else with same experience ????
My 2 cents.
========================================
Message du 17/09/12 15:51
De : "Pete"
A : [log in to unmask]
Copie à :
Objet : Re: [DC] Vias under a QFN package (Thermal Refief)
larger holes actually increase solder wicking, especially with lead free. go smaller!
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