Thanks, great info.I saved in my design note file.
----- Original Message -----
From: "Richard D. Stadem" <[log in to unmask]>
To: [log in to unmask]
Sent: Thursday, March 19, 2009 10:37:18 AM GMT -05:00 US/Canada Eastern
Subject: Re: [TN] Traces and vias under components
Ok, I have finally seen enough emails on this subject to respond.
First, many designs will not work with trace connections from chip cap
and chip resistor pads going back under the component, because it
essentially changes the rated capacitance or induces an RC network into
the circuit. For certain high-speed RF circuits this is especially true.
Second, soldermask is not defined as an insulator per IPC standards.
Solder mask skips and discontinuities are allowed. Therefore the concern
of entrapped flux under chip components creating a high-resistance or
high-impedance short or path is very real, and has been documented many
times.
Third, the tented soldermask height is difficult for any PWB fabricator
to control, and as such it quite often presents a little bump right
between the pads. This leads to poor gasketing of the stencil during the
printing process, which in turn leads to excess solder, bridging, solder
balls, etc. Vias further away from the open apertures are isolated from
the paste bricks, and are thus not an issue.
For these reasons many companies adopted the design rule of no vias
under or near chip pads, period.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Pete Houwen
Sent: Thursday, March 19, 2009 8:13 AM
To: [log in to unmask]
Subject: Re: [TN] Traces and vias under components
This is when it's good to be captive. I get to make the dumb rules for
myself!
If that's what they want. that's what they get. Say no, they'll find
someone who will say yes. And if it takes more layers to route,
consider it an economic stimulus for the fab shops. If the planes are
so fragmented that they fail FCC or have SI problems, you'll get paid
for a few more turns of the board.
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