Bob,
One reason a safe place for traceability markings must be specified is
that they are usually in copper. The fabricator does not know one
voltage from another, and will place the markings wherever there is
space to do so. If your board had high voltage conductors on the board,
his traceability marking could very well violate the minimum electrical
space between those conductors. Unless you wanted the board to glow in
the dark, I would advise providing the fabricator with a safe spot to
place the markings. Dimension it with a loose one place decimal.
Gary
Wilson, Bob wrote:
> The drawing revision description block shall identify the specific
> changes
> made. It is not acceptable to just reference to the Engineering Change
> Proposal
> (ECP)or other engineering document that initiated the change
> This is ridiculous. Some changes I've seen require multiple pages in the
> ECN or EO (Notice or Order) for the schematic, fab and/or assembly. The
> path should be ECP or ECR (Engineering Change Request) and then an
> approved ECN or EO, with effectivity serial numbers and effectivity
> dates, detailed changes and reasons for change. How the heck does that
> fit in a revision block?
>
>
> The initial release of a design will be given a (-) revision. Subsequent
> Revisions will be assigned A,B,C,etc, leaving out I,O,Q,X,S,Z
> This is not a 'shall'-it is company philosophy. I've seen this all over
> the map. Revisions 1, 2, 3 or X1, X2, X3 for prototypes and A. B, C for
> released...with no "-" in a rev block.
>
> Whenever the drawing, or computer transferrable media, requires a
> revision,
> The description shall identify whether the revision impacts form, fit,
> function
> When would a change not affect form fit or function? A spelling error
> correction, maybe?
>
> Three fiducials (or registration targets) shall be located on grid and
> on
> each layer of data pattern. Each additional layer or data pattern shall
> have fiducials
> located at the same points which, shall register with each other, layer
> to layer.
> First I've heard of each layer. If I can fit them, maybe.
>
> The method of excising individual boards shall be included in the
> assembly
> Pallet description.
> We leave that up to the buyers. Some CM assemblers prefer routed out
> boards some prefer paneled either rat bites or v-score.
>
> Unplated through hole patterns, especially tooling and mounting holes
> (board
> mounting holes, interface connector mounting holes, board top
> plate/mounting
> bracket mounting holes, etc.) are generally drilled in separate drilling
> operations as one of the last fabrication operations. They shall be
> explicitly
> dimensioned and toleranced, even if they occur on grid.
> I agree only insofar as required for inspection. As designers we don't
> dictate the fabrication method or what's first or last. (Although it
> helps if you know how they might approach it). If I tell them I want a
> hole at X, Y dimension XX diameter with YY tolerance, I don't care if
> they use a laser or a sharpened stick.
>
> The fabrication drawing shall specifically indicate the location for the
> date code, fabricator's I.D. and UL marking, user's cage code, ESD
> symbol and all other
> required traceability markings.
> This is also ridiculous. They know what they're doing. Maybe specify
> that markings must be visible after components are loaded.
>
> A note on the fabrication data set shall specify the acceptable bow and
> Twist requirements
> Agreed
>
> Anyone who writes back can say they helped a standards development
> committee!
> See how easy this stuff is?
>
> If you are lucky enough to attend APEX/EXPO, wander into a real meeting.
> Here are the choices:
> http://www.ipcapexexpo.org/Std.aspx
>
> Just trying to hang on to my job. They'd throw me out if I asked to go
> to APEX.
>
> Jack (aka "the new guy")
>
> Bob Wilson
> E/M Designer, CID+
> SpectraSensors, Inc.
> 11027 Arrow Route
> Rancho Cucamonga, CA 91730
> (909) 948-4110
> www.spectrasensors.com
> www.ipc.org
>
>
>
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