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January 2008

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Subject:
From:
Yuan-chia Joyce Koo <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Yuan-chia Joyce Koo <[log in to unmask]>
Date:
Mon, 7 Jan 2008 08:21:08 -0500
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I agree with Brian.  normally the high heat reflow is better... if  
you have insufficient reflow or the flux is dissociated during the  
transport or what ever the reason, you might have a problem.  As for  
OEM data, is it the real process data or the exit certificate?  if it  
is certificate, any rework that caught in the process would not  
shown... (my 2 cents)...jk
On Jan 7, 2008, at 2:09 AM, Brian Ellis wrote:

> I haven't entered this thread up to now because Doug said it all,  
> but I
> disagree with the notion that contamination testing is unnecessary  
> with
> RMA fluxes, for several reasons.
>
> 1) How do you know what levels and types of contamination were present
> on the bare board and components before soldering?
>
> 2) How do you know whether all the halides in the flux have been
> deactivated?
>
> 3) How do you know whether the cleaning process has not removed the
> rosin but left the activators?
>
> 4) How do you know that metal halides have been removed?
>
> Brian
>
> - bogert wrote:
>> January 6, 2008
>> If the solder flux used is RMA or equivalent, is there any real  
>> benefit to doing a cleanliness test?  I have reviewed OEM  
>> cleanliness test resords at several OEMs and the data I reviewed  
>> shows folks rarely, if ever fail this test.
>>> From: Graham Collins <[log in to unmask]>
>>> Reply-To: TechNet E-Mail Forum <[log in to unmask]>,  
>>> [log in to unmask]
>>> To: [log in to unmask]
>>> Subject: Re: [TN] specifying board cleanliness
>>> Date: Thu, 3 Jan 2008 11:09:58 -0400
>>>
>>> Happy New Year Phil!
>>> Well, "it depends"...
>>>
>>> First question is how clean do you need them to be?  Depends on the
>>> application and environment.  Second question is what sort of  
>>> assembly
>>> process the CM is using - if "no clean" then they will be  
>>> justifiably
>>> opposed to cleanliness testing.
>>>
>>> The generic callout that we most commonly see on drawings is  
>>> "clean per
>>> J-STD-001 C-22" - which translates into clean the assembly, both  
>>> sides,
>>> and then do an ionic contamination test with a upper limit of 1.56
>>> micrograms / cm2 NaCl equivalent contamination.  I'm not sure why
>>> J-STD-001 gives an option to only clean one side - never seen that
>>> process in use.  Anyway, a starting point...
>>>
>>> regards,
>>>
>>> Graham Collins
>>> Halifax Production Engineering
>>> L-3 communications Electronic Systems
>>> (902) 873-2000 ext. 6215
>>>
>>>
>>> -----Original Message-----
>>> From: TechNet [mailto:[log in to unmask]] On Behalf Of Phil Nutting
>>> Sent: Thursday, January 03, 2008 10:45 AM
>>> To: [log in to unmask]
>>> Subject: [TN] specifying board cleanliness
>>>
>>> Good Morning and Happy New Year to All,
>>>
>>> Let me start by confessing my ignorance relative to cleanliness of
>>> circuit boards.  We have no idea what numbers to specify that fit  
>>> into
>>> the IPC testing methods for board cleanliness.  If I tell my CMs  
>>> to make
>>> the boards clean, it would be good to specify a target value and  
>>> or test
>>> method.
>>>
>>> Can someone give me some guidance on how to chose these  
>>> specifications?
>>> What are worth while tests and which ones are window dressing?
>>>
>>> I've read through some of the IPC tests methods and my head hurts.
>>>
>>> Thanks in advance,
>>>
>>> Phil Nutting
>>>
>>> Note: All the information contained in this e-mail and its  
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