Raja,
The database you send to your fabricator should contain 1:1 soldermask
clearances. Your master drawing should contain a note that gives
permission to resize the mask for minimal mask to land clearance. But,
don't forget to include a note to manufacture in accordance with
IPC-6011/12. These IPC performance specifications specify the allowable
variation of the soldermask application. In other words, clearances not
to expose adjacent copper, amount of soldermask allowed on lands, skips,
etc.
Regards,
Gary Ferrari
FTG Circuits
Director, Technical Support
860-350-9300
No Name wrote:
> Hi All,
>
> I am recently shifted into PCB design filed; interesting field off course!!! satisfied being a part of product development.
> Now started learning the reason for each task I perform. Hope I can get more suggestions from expertise here :-).
>
> I understand the reason that slodermask is used for better solderability, but I want to know why we provide certain clearance like 0.005" or 0.004" more than pad size, sometimes I see soldermask missing (say on BGA). Any problems you have experienced due to larger or smaller soldermasks?
>
> Is there any specific standards or calculation used for soldermask creation based of padstack,Assembly process say wave soldering or reflow soldering? How IPC calculates this? I have IPC SM782.
>
> Awaiting for your suggestions.
>
> Thanks,
> Raja.
>
>
> Check out AOL.com today. Breaking news, video search, pictures, email and IM. All on demand. Always Free.
>
> ________________________________________________________________________
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