Silicon Valley Chapter of the IPC Designers Council
Our next meeting will take place on Tuesday, September 12, 2006.

Location:
Mentor Graphics
1001 Ridder Park Drive, San Jose, CA
Tuesday, September 12
Time: 11:30AM - 1:30PM
$1 for chapter members; $5 for visitors
DOOR PRIZE: $25 IPC Publication Certificate

RSVP required > send to [log in to unmask]



  Caution! High Speed Zone Ahead.
  By David Hoover (Sr. FAE Multek, Inc.)
  and Leena Gulia (Park Electrochemical Corp – aka, Nelco Laminates)
  This Presentation / Discussion will cover two main topics.

   Controlled Impedance
  (High-Speed Design Guidelines and Capabilities)

   Low Loss Materials
  (Including Low Loss Substrates and High Frequency)
        This presentation/discussion will cover many of the
  typical issues encountered with modeling, specifying, and testing Controlled Impedance (CI) PCBs. Along with a list of conditions when a PCB may require CI, this presentation/discussion will cover the various techniques used today to model CI including from the Motorola MECL formulae all the way up to 3D Field Solvers. We will discuss the “what” and “where” variables that contribute to modeling variation between software simulations. Examples will be shown on how entry variables can effect the calculated results based on the modeling software parameters. Additionally, we will cover common Dk ranges found in standard Epoxy based FR-4 along with typical Er expectations found at higher frequencies. We will discuss low loss substrates along with what is currently being used to gain higher data rates (10 and up to 40 GHz) on multilayer PCBs. The cost implications of switching between material sets will also be discussed.

  ~  ~  ~  ~  ~

  Please RSVP by Friday (9/8/05) > send to [log in to unmask]

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