The difference is in the inspection in Table 3-3 is for a visual
assessment of the PCB.  Table 3-6 is for the microsection analysis
assessment.  In this inspection, conditions that reduce the copper
thickness below the minimum are evaluated as voids.  This allows for
smaller conditions, that otherwise would not be seen by surface
examination, to be assessed for size and frequency.  The holes being
microsectioned post-stress are also vias that in general can not be
evaluated under the visual assessment conditions.  

Jeffrey Bush
Director, Quality Assurance and Technical Support

VERMONT CIRCUITS INCORPORATED
  76 Technology Drive - POB 1890
    Brattleboro, Vermont 05302
      Voice: 802.257.4571.21 Fax: 802.257.0011
           http://www.vtcircuits.com
 

-----Original Message-----
From: Deborah Schepis [mailto:[log in to unmask]] 
Sent: Wednesday, March 30, 2005 2:31 PM
To: [log in to unmask]
Subject: [TN] Plating void criteria in IPC-6012

Hi folks!

I see what seems to be a contradiction in plating void criteria in the
IPC-6012 for Class 3.  Table 3-3 (Plating and Coating Voids Visual
Examination) says "none" for copper voids allowed.  Table 3-6 (Plated
Hole
Integrity After Stress) says "one void allowed per specimen provided the
additional microsection criteria of 3.6.2.2 are met."  Since voids are
not
created by the stress, why would they be allowed after stress (in cross
section) but not before (seen visually)?

Thanks,

Debbie

Deborah S. Schepis
Quality Engineer
Endicott Interconnect Technologies
(607) 755-3152
email: [log in to unmask]

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