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January 2005

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(Leadfree Electronics Assembly Forum)
Date:
Tue, 11 Jan 2005 10:46:51 EST
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Hello Pascal,

In a message dated 1/11/2005 9:31:28 AM Eastern Standard Time, 
[log in to unmask] writes:
Do we really depend on reliability ? Sure since we need long life (15 years)
components and boards, less sure because application cycle looks "low
stressing" (maybe 2 cycles per day, Tmin=20°C, Tmax=-70°C, ramp up or down
about 0.5°C/min.
In what used to be called Class II and III applications in IPC standards, 
end-users have fairly high reliability requirements, much more so for Class III.
0.5C/min is slow enough to allow for creep of both SnPb and SAC during ramps. 
Dusek et al. (NPL) gave an interesting paper on ramp effects at SMTAI'04, 
with thermal cycling results for SAC assemblies showing the more damaging effect 
of profiles with slow ramps.  This is also verified by hysteresis simulations 
for SAC solder joints.


Don't you think we can proceed by comparaison to SnPb accelerated test life
but with low stress (-20°C - 120°C as proposed by Gûnther, or 0°C - 100°C ),
considering that SAC is more reliable than SnPb for these low stess
conditions ?
The relative ranking of alloys under the above conditions, with typically 
short dwell conditions, is likely to be reversed in applications with long dwell 
periods. 
This has to be looked at on a component and case-by-case basis.  The only 
quick way to find out at this point is by hysteresis loop simulation, using 
ratios of strain energies per cycle to get an estimate of acceleration factors.

With best regards,
Jean-Paul

__________________________
Jean-Paul Clech
[log in to unmask]
http://jpclech.com/ 

EPSI Inc.
P.O. Box 1522, Montclair, NJ 07042, USA
tel: +1 (973)746-3796
fax: +1 (973)655-0815

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