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October 2004

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Subject:
From:
"Brooks,Bill" <[log in to unmask]>
Reply To:
(Designers Council Forum)
Date:
Thu, 14 Oct 2004 19:30:25 -0700
Content-Type:
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text/plain (96 lines)
Hi Robert,

This is the note I use to cover board flatness and bow and twist for surface
mount components on glass/epoxy laminate multilayer boards.


BOW AND TWIST SHALL NOT EXCEED 0.75% (.00075 IN PER IN) IN ACCORDANCE WITH
IPC-A-600F FOR SURFACE MOUNTED BOARDS WHEN MEASURED USING IPC-TM-650, METHOD
2.4.22.


I hope that helps...

Best regards,

Bill Brooks - KG6VVP
PCB Design Engineer , C.I.D., C.I.I.
Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510
http://www.dtwc.com
http://pcbwizards.com


-----Original Message-----
From: Harter, Robert [mailto:[log in to unmask]]
Sent: Thursday, October 14, 2004 4:05 PM
To: [log in to unmask]
Subject: [DC] IPC Flatness and Callout of Standards to Use in Fab Notes.

Hi All,



I am writing to ask what is the IPC tolerance for how flat a PCB must be
and what callout should I use in my Fab Notes?  This PCB is going to be
part of an RF Filter module that will be SMD.  I made an inquiry a few
weeks ago about best practices to employ for designing a flat board that
has a 25mil 6010 top core and 2 FR-4 cores for control routing.
Thank-you all again for the great timely advice on that question, now
I'm just trying to make sure the Fab house and I are on the same page.





Bob Harter, Jr.

PCB Designer

Paratek Microwave, Inc.

6935 G Oakland Mills Rd.

Columbia, MD 21045

PH# (443)259-0140 x278

CP# (443)739-8407

WWW.PARATEK.COM <http://www.paratek.com/>




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