It is dangerous to oversimplify on this issue.
Some high frequency chip are very large. It depends upon how the die is
designed and functionally partitioned.
0.013nm transistor state maintenance requires very small amts of
capacitance, but at switching speeds of a GHz or more, power dissipation can
be very high, even with low supply voltage.
Power dissipation in CMOS is proportional to frequency, the capacitive load,
and the square of the supply voltage level.
Large high frequency chips suffer from RC time delay effects, not skin
effect, because the conductors are thinner than the "skin" for the metals
considered (Cu and Al, and W vias). This is why advanced ICs are moving to
the Cu - Low K dielectric constructions. So since a signal chip-crossing
event will suffer from RC time delay, designers try to partition the chip to
minimize this effect, which also benefits simply by making the die smaller
with transistor shrinks.
Regards,
Leo
------------------------------------
Leo M. Higgins III, Ph.D.
Director of Applications Engineering / ASAT Inc.
[log in to unmask]
3755 Capital of Texas Hwy-So
Suite 100
Austin, TX USA 78726
tel: 512-383-4593
fax: 512-383-1590
mobile: 512-423-2002
------------------------------------
-----Original Message-----
From: Saravanan [mailto:[log in to unmask]]
Sent: Friday, June 11, 2004 7:06 AM
To: [log in to unmask]
Subject: [TN] Relation between physical size and frequency??
Hi,
Could some one explain me quantitatively why the physical size of an
electronic chip reduce in size as the operating frequency increases. I
remember the P2 processor is conspicuously bigger than the latest P4
processor. What is the reason behind?
Regards,
Saravanan.K
---------------------------------------------------
Technet Mail List provided as a service by IPC using LISTSERV 1.8e
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt or (re-start) delivery of Technet send e-mail to
[log in to unmask]: SET Technet NOMAIL or (MAIL)
To receive ONE mailing per day of all the posts: send e-mail to
[log in to unmask]: SET Technet Digest
Search the archives of previous posts at: http://listserv.ipc.org/archives
Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16
for additional information, or contact Keach Sasamori at [log in to unmask] or
847-509-9700 ext.5315
-----------------------------------------------------
---------------------------------------------------
Technet Mail List provided as a service by IPC using LISTSERV 1.8e
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL)
To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest
Search the archives of previous posts at: http://listserv.ipc.org/archives
Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
-----------------------------------------------------
|
