Hi Dave,

The relevant EIA spec is available from this location:
http://www.chipro.com/PDF%20Files/EIA-481-B.pdf

Best regards,

Daan Terstegge
http://www.smtinfo.net


----- Original Message -----
From: "Dave Chapman" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, June 21, 2004 5:34 PM
Subject: Re: [TN] Component packaging


> -----Original Message-----
> From: Dave Chapman [log in to unmask]
> Sent: Monday, June 21, 2004 10:19 AM
> To: [log in to unmask]
> Subject: [TN] Component packaging
>
> Is there a IPC, JEDEC or EIA document that references how ICs should be
> packaged when on tape and reel? Specifically pin 1 locations or package
> angle as we know it in SMT. I've been through ANSI/IPC-SM780 (March of
1998)
> but not much there.
> Dave Chapman
>
>
>
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