Greetings all,

I have a customer who is doing an impedance design for Intel and he has no
previous impedance experience.  This is the information I have.

- double sided board
- target impedance 50ohm
- signal line 5mil wide, spaced 5mil from "ground" trace and this pair of
traces should be spaced a minimum of 20mil from adjacent traces.

This is what he was given from Intel.  I am using an older Polar model
(CITS25 calculator) which does have models for co-planar designs but from
what I can tell they assume that the signal trace is sandwiched between
ground (return lines) on both sides.  Is this a correct interpretation?  Is
it possible to model the design as described above?

While we have some experience with controlled impedance I have no experience
with the aforementioned design and could use some assistance.

Best Regards
John Parsons

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