Greetings all, I have a customer who is doing an impedance design for Intel and he has no previous impedance experience. This is the information I have. - double sided board - target impedance 50ohm - signal line 5mil wide, spaced 5mil from "ground" trace and this pair of traces should be spaced a minimum of 20mil from adjacent traces. This is what he was given from Intel. I am using an older Polar model (CITS25 calculator) which does have models for co-planar designs but from what I can tell they assume that the signal trace is sandwiched between ground (return lines) on both sides. Is this a correct interpretation? Is it possible to model the design as described above? While we have some experience with controlled impedance I have no experience with the aforementioned design and could use some assistance. Best Regards John Parsons --------------------------------------------------- Technet Mail List provided as a service by IPC using LISTSERV 1.8e To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315 -----------------------------------------------------