At 03:18 PM 4/29/2002 -0400, Marsico, James wrote:
>Dwight, just out of curiosity, why not plate ALL of the vias with 3 mils of
>copper.  Wouldn't this be cheaper than drilling, plating, drilling and
>plating again?

That would put some pretty extreme copper thickness on the outerlayer.  No
way we could maintain the fine lines and spaces we use on the outer
layers.  The "buttons" from the selective plate are sanded off prior to
drill and plate of the other vias.

Dwight


>Jim Marsico
>Senior Engineer
>Production Engineering
>EDO Electronics Systems Group
>[log in to unmask] <mailto:[log in to unmask]>
>631-595-5879
>
>
>         -----Original Message-----
>         From:   Dwight Mattix [SMTP:[log in to unmask]]
>         Sent:   Monday, April 29, 2002 1:26 PM
>         To:     [log in to unmask]
>         Subject:        Re: [TN] Via Plug
>
>         At 11:29 AM 4/24/2002 -0700, John Foster wrote:
>         >Thanks Jim
>         >
>         >Did you do this extra plating selectively. Or did you just
>overplate the
>         >whole PCB.
>
>         We have a lot of applications where we spec thermal vias to be
>selectively
>         plated to a minimum of 3 mils annular copper.
>         The fabricator drills the thermal vias and selectively plates to 2
>         mils.  Then they drill and (plate the rest of the board to 1 mil
>(adding to
>         thermal via copper as well).
>
>         It's way more effective at heat transfer than any conductive epoxy
>we've
>         tried.   This approach is also very effective at controlling solder
>wicking
>         to the bottom of the board -- we'll use it sometimes when we don't
>have a
>         thermal problem but just want to control solder flow into unplugged
>fields
>         of gnd vias (saves masking backside).
>
>         Dwight
>
>
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