TECHNET Archives

1996

TechNet@IPC.ORG

Options: Use Monospaced Font
Show Text Part by Default
Show All Mail Headers

Message: [<< First] [< Prev] [Next >] [Last >>]
Topic: [<< First] [< Prev] [Next >] [Last >>]
Author: [<< First] [< Prev] [Next >] [Last >>]

Print Reply
Subject:
From:
"Nancy Nelson" <[log in to unmask]>
Date:
Thu, 28 Mar 96 08:38:24 CST
Content-Type:
text/plain
Parts/Attachments:
text/plain (12 lines)
Is there a Standard amount of Test Point Coverage at the PCB Bare 
Board Supplier during Electrical Test in which an NRE setup and 
100% Electrical Test of PCB's was charged.

What is the chance of Escape associated with Electrical Test?

Thanks in advance for any help given.

[log in to unmask]



ATOM RSS1 RSS2