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Subject:	Re: Placement of Chip resistors deposited element
From:	Alex Krstic <[log in to unmask]>
Reply To:	TechNet E-Mail Forum.
Date:	Mon, 29 Jan 2001 10:27:45 -0700
Content-Type:	multipart/alternative
Parts/Attachments:	text/plain (2255 bytes) , text/html (17 kB)

Thanks Ed.  I trust you had a chance to read Jack Crawfords reply.  While I see
the difference in my interpretation of Rev C, it doesn't make  me feel better
that Rev B called it a defect.  I also misquoted the section number it should
have read 6.4.3.2

Alex Krstic
NovAtel Inc.

-----Original Message-----
From: Ed Valentine [mailto:[log in to unmask]]
Sent: January 25, 2001 8:06 PM
To: TechNet E-Mail Forum.; Alex Krstic
Subject: Re: [TN] Placement of Chip resistors deposited element

Alex - My two cents:

The bottom line is the power dissipation of the chip resistor in the circuit.
Assuming for argument's sake, that the resistor is an 0805 with a rating of 1/10
watt, and the resistor is dissipating near the full wattage, the resistor
element (on glass laminate) needs to be face up. Glass laminate, like FR4, is a
good thermal insulator. If the power dissipation is, for argument's sake, less
than 1/2 the rated wattage, then it shouldn't make any difference, and the
resistor should be a process indicator. If the resistor is mounted on a ceramic
(Alumina) substrate, then the resistor can be mounted either way with virtually
no effect, except aesthetics. Ceramic (Alumina), unlike FR4, is a good thermal
conductor.

Ed Valentine
Electronics Manufacturing Solutions
8612 Mourning Dove Road, Raleigh, NC 27615
Phone: (919) 270-5145, Fax: (919) 847-9971
Email: [log in to unmask] <mailto:[log in to unmask]>
Website: http://www.ems-consulting.com <http://www.ems-consulting.com>
----- Original Message -----

From: Alex Krstic <mailto:[log in to unmask]>
To: [log in to unmask] <mailto:[log in to unmask]>
Sent: Thursday, January 25, 2001 4:12 PM
Subject: [TN] Placement of Chip resistors deposited element

Hello all.  We recently received some boards with some of the chip resistors
placed with their resistive elements towards the board.  J-STD-001B and C view
this as violation for both Class 2 and Class 3.  However when you compare this
with IPC-A-610C it is only a process indicator for Classes 2 and 3.  The
relevant sections are

J-STD-001C

6.4.2.2 Devices with External Deposited Elements

IPC-A-610C

12.3.2 Chip Components - Termination Variations - Deposited Electrical Elements
- Mounting Upside Down.

So.....who is correct?  Does it matter?

Alex Krstic

NovAtel Inc.

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