Jim-
As always, depends on the application.
I'd certainly consider using a complete via fill. It's probably not
very expensive if done AFTER plating. The vendor would plate, fill,
planarize, then image, develop, and etch the conductors (assuming this
is a panel plating job). With this process, your vendor would not have
to go through 2 plating cycles. As for the bottom side testing, you
would still have the same annular ring to probe to, assuming that's what
you're hitting now. If you're not probing the ring, then I guess you're
going for the via sidewall, which seems a bit hard on the vias. I'm
presuming you don't want the boards to be re-designed to have a separate
probe pad adjacent to the via, but even a 5x5 mil pad is still often
probe-able.
If you want to live with what you've got, the 3V biased condition you
mention is not "on the shelf" as far as the pc board goes, because the
bias voltage will provide the electro-motive force which drives the
corrosion process. Hence you will probably want to do HAST testing (a
carefully engineered test to simulate the full operational life and
beyond) to validate that the entrapped flux residue will not be a
problem. And then you will also need to re-validate if you're pcb
vendor changes processes or chemistries. (The option of plugging the
vias starts looking cheaper all the time!)
Running the boards with the HASL side down is probably worse than HASL
side up since the volatile flux products will be lighter than the solder
and thus will want to go up to escape, so if they are tented on the top
with solder mask, the stuff is unlikely to escape. It really won't
escape that situation no matter what. You need a cleaning agent to
remove it, and getting sufficient cleaning agent to the problem area
inside of a "tented" 8 mil via is a very tall order.
Good Luck,
Wayne Thayer
>>> [log in to unmask] 11/6/2006 5:06:29 pm >>>
How long would it take for flux from a HASL finish process trapped in
a
via to cause a defect? The PCB is .050 thick with 8 mil vias.
Regular
FR4 material for SnPb solder process. 8 mil vias, 4 layer, 1/2 oz all
layers with 1 oz plate up on outer layers. the board is fabricated to
IPC Class 2. The board is all SMT components on the top side only.
We
had been tenting both sides of the board with primary Solder mask, but
have been having problems with shorts due to in complete coverage of
the
via. We tried a Post HASL plug process, but have had problems with
bumps under a 64 pin QFN package. The reason for the problem is that
sometimes the vias are filled with HASL other times open, which makes
the caps inconsistent causing assembly issues. So we are considering
going back to tenting the bottom and pre-HASL capping the vias that
are
causing shorts. Only the vias under the QFN need to be fully covered.
The PCB Quality Engineer at our CM tells us that tenting both sides
prior to HASL would not be a big concern, but since 35 vias are in
test
points on the bottom, both sides on these vias can't be covered before
HASL and covering only one side can create a situation where flux from
the HASL process which contains corrosive stuff is trapped in the via
by
the HASL. The product has a shelf life of about 2 years with 3V
applied
(if it stays on the shelf for that long) and only needs to operate for
3
days. Do I really need to be concerned about this? When the PCBs go
through a reflow oven with the HASL side of these vias facing down,
wouldn't this reflow the HASL and allow gravity to work in our favor?
The other option is to do 100% non-conductive fill and
re-planerization
after plating, but this a more expensive process. Also, changing
board
finishes would make the post finish cap process more predictable, but
that is not an option right now.
Jim Verrette
Electrical Engineer
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