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May 1999

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Subject:
From:
"Joy, Stephen C" <[log in to unmask]>
Reply To:
DesignerCouncil E-Mail Forum." <[log in to unmask]>, "Joy, Stephen C" <[log in to unmask]>
Date:
Fri, 21 May 1999 14:08:20 -0700
Content-Type:
text/plain
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Ron,
Where does the antipad contribution come in?
Steve

-----Original Message-----
From: Ronald Giachetti [mailto:[log in to unmask]]
Sent: Friday, May 21, 1999 9:52 AM
To: [log in to unmask]
Subject:


An equation for the estimating the number of layers to route a BGA:

# of layers = ( (n/2)-((G-Db-s)/(L+s))+1 / ((G-Dv-s)/(L+s))+1 ) + 1

where

L = line width
Dv = via pad size
G = I/O pitch
s = line spacing
Db = contact pad size
n = # of I/O

I saw this equation in a technical report, it is originally attributed to
Dr. C. Chao at HP Laboratory.  I
know somebody who has validated with some of their boards.  I'll be
interested in finding out how it works
with yours.

Ron Giachetti
Department of Industrial & Systems Engineering
Florida International University
Miami, FL 33174
[log in to unmask]


[log in to unmask] wrote:

> Looking for information on designing a printed circuit card using  several
> 256-pin micro-BGAs.  The pin scheme is a 16 X 16 matrix with 1mm pad
pitch.
> Issues include:
>
>         Routing approaches (how to best achieve routability).
>         Number of layers required.   Is there a formula to determine this?
>
> Any kind of information anyone can provide would be greatly appreciated.
> Thank you,
>
> Connie Lauterbach
> Sr. PCB Designer
> Evans & Sutherland
> Salt Lake City, UT
>
> [log in to unmask]
>
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